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PDF TDA9989 Data sheet ( Hoja de datos )
| Número de pieza | TDA9989 | |
| Descripción | 150 MHz Pixel Rate HDMI 1.3a Transmitter | |
| Fabricantes | NXP Semiconductors | |
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TDA9989
150 MHz pixel rate HDMI 1.3a transmitter with 3 × 8-bit video
inputs and CEC support
Rev. 02 — 11 June 2009
Product data sheet
1. General description
The TDA9989 is a very low power and very small size High-Definition Multimedia Interface
(HDMI) 1.3a transmitter. It is backward compatible DVI 1.0 and can be connected to any
DVI 1.0 and HDMI sink.
This device is primarily intended for mobile applications like Digital Video Camera (DVC),
Digital Still Camera (DSC), Portable Multimedia Player (PMP), Mobile Phone and Ultra
Mobile Personal Computer (UM PC) where size and very low power are mandatory for
battery autonomy.
It allows mixing 3 × 8-bit RGB or YCbCr video stream with a pixel rate up to 150 MHz
together with one S/PDIF or one I2S-bus audio streams with an audio sampling rate up to
192 kHz.
In order to be compatible with most applications, the TDA9989 integrates a full
programmable input formatter and color space conversion block. The video input formats
accepted are YCbCr 4 :4 : 4 (up to 3 × 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to 2 × 12-bit)
and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1 × 12-bit). In case of ITU656-like
format, the input pixel clock can be made active on one (SDR mode) or both edges (DDR
mode).
This device provides additional embedded feature like CEC (Consumer Electronic
Control). CEC is a single bidirectional wire that transmits CEC commands (like Standby
from remote control) over the home appliance network connected through this wire. This
eliminates the need of any additional device to handle this feature thus improving BOM
(Bill Of Materials) of the whole system and enable the connected devices (CEC enabled)
to be controlled by only one remote control.
The TDA9989 supports xvYCC HDMI 1.3a feature.
It can be switched to very low power Standby or Sleep modes to save power when HDMI
is not used.
The TDA9989 includes a true I2C-bus master interface for DDC-bus communication for
EDID reading.
This device can be controlled or configured via I2C-bus interface.
1 page  
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TDA9989
HDMI 1.3a transmitter with CEC support
6. Pinning information
6.1 Pinning
ball A1
index area
A
B
C
D
E
F
G
H
TDA9989
12345678
001aai443
Transparent top view
Fig 3. Pin configuration (TFBGA64)
6.2 Pin description
Table 2. Pin description
Symbol
Pin Type[1]
ACLK
H5 I
AP0 G5 I
AP1 F5 I
HPD
E6 I
EXT_SWING E7
O
DSDA
DSCL
VCLK
HSYNC/HREF
VSYNC/VREF
DE/FREF
CSCL
CSDA
INT_HDMI
F6
F7
D4
F4
G4
H4
B5
A5
B6
I/O
I
I
I
I
I
I
I/O
I/O
TX0−
TX0+
TX1−
E8 O
D8 O
C8 O
Description
audio clock input
audio port 0 input
audio port 1 input
hot plug detect; 5 V tolerant
TMDS output swing adjustment; place resistor
(REXT_SWING = 10 kΩ ± 1 %) between this pin and analog
ground.
DDC-bus data input/output; 5 V tolerant
DDC-bus clock input; 5 V tolerant
input video pixel clock
input horizontal synchronization or reference input
input vertical synchronization or reference input
data enable or field reference input
I2C-bus clock input; 1.8 V to 3.3 V tolerant
I2C-bus data input/output; 1.8 V to 3.3 V tolerant
interrupt HDMI output (open-drain); this pin is used as Dual
function pin selectable through I2C-bus. In calibration mode
only this pin is used as input for 10 ms ± 1 % calibration pulse.
In operation mode this pin is used to warn the external
microprocessor that a special event has occurred for HDMI or
CEC
negative data channel 0 for TMDS output
positive data channel 0 for TMDS output
negative data channel 1 for TMDS output
TDA9989_2
Product data sheet
Rev. 02 — 11 June 2009
© NXP B.V. 2009. All rights reserved.
5 of 48
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TDA9989
HDMI 1.3a transmitter with CEC support
Table 5. TDA9989 input/output capability …continued
Bit setting
Internal port
MIRR_E = 1
SWAP_E = 5
VP[7]
VP[6]
VP[5]
VP[4]
MIRR_F = 1
SWAP_F = 4
VP[3]
VP[2]
VP[1]
VP[0]
To be mapped to
VPA[4]
VPA[5]
VPA[6]
VPA[7]
VPA[0]
VPA[1]
VPA[2]
VPA[3]
When input ports are not used, it is possible to map them to internal ground via the
I2C-bus with the appropriate set of registers ENA_VP_0, ENA_VP_1 and ENA_VP_2 on
page 00h.
TDA9989_2
Product data sheet
Rev. 02 — 11 June 2009
© NXP B.V. 2009. All rights reserved.
11 of 48
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA9989.PDF ] | |
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