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PDF IP1000ALF Data sheet ( Hoja de datos )
| Número de pieza | IP1000ALF | |
| Descripción | Gigabit Ethernet NIC Single Chip | |
| Fabricantes | IC Plus | |
| Logotipo |  |
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IP1000A LF
Preliminary Data Sheet
Gigabit Ethernet NIC Single Chip
Features
PCI & DMA Features
– PCI Specification Revision 2.3 compliant
– 32-bit, 33/66MHz bus master capability
– Efficient DMA operation maximizes PCI
band-width utilization
– 1 Terabyte (40 bit) address space
– Scatter, gather transmit/receive DMA
– Transmit "interrupt-less" mode of
operation
– Receive frame priority interrupts
– Receive interrupt coalescing
FIFO Features
– No external memory required
– Receive FIFO flow control thresholds
– Configurable TX/RX FIFO
MAC Features
– IEEE 802.3z, 802.3x compliant
– IEEE 802.1p, 802.1Q compliant
– 1000Mbps, 100Mbps, 10Mbps triple
speed, half/full duplex operation
– Transmit and receive back to back frames
at full wire speed
– Half duplex carrier extension and packet
bursting
– Asymmetric/symmetric flow control
– VLAN tag insertion/removal
– VLAN tagged frame filtering
– IPV4/6, TCP, UDP checksum calculation/
verification
– 802.3 MIB statistic register sets
– 64-bit hash table for multicast frame
filtering
– Jumbo frame support for transmit/receive
– Big-endian
Phsical Layer Features
– Fully integrated IEEE 802.3ab compliant
1000BASE-T, 100BASE-TX and
10BASE-T port
– DSP receiver includes feed-forward
equalizer, decision feedback equalizer,
echo canceller, crosstalk canceller, and
baseline wander correction
– 802.3ab compliant Auto-Negotiation for
automatic speed, duplex, and
master/slave configuration
– Automatic MDI/MDI-X crossover function
and polarity correction
– Automatic pair skew adjustment
– PHY management registers
– Smart Cable Analyzer (SCA™)
– Smart speed downshift
– APS(Auto Power Saving)
a. Power Saving with Link status detecting
b. Keep only MAC alive through
software setting
Power Management, EEPROM and Package
– WakeOnLAN support
– ACPI Revision 1.0 compliant
– 1.8/3.3V CMOS with 5V tolerant I/O
– EEPROM 93C46 support
– Optional boot from serial ROM support
– 128-pin LQFP with e-PAD package
Support Lead Free package (Please refer to
the Order Information)
General Description
The IP1000A LF is a truly 10/100/1000Mbps
Gigabit Ethernet NIC single chip which it
incorporates a 32-bit PCI interface with bus
master support. It is manufactured using standard
digital CMOS process and contains all the active
circuitry required to implement the physical layer
functions to transmit and receive data on standard
CAT5 unshielded twisted pair cable.
The IP1000A LF is designed for use in a variety of
applications including workstation NICs, and other
systems utilizing a PCI bus.
The IP1000A LF includes a 32-bit PCI bus
interface, IEEE 802.3 compliant MAC, transmit
and receive FIFO buffers, IEEE 802.3 compliant
10BASE-T, and 100BASE-TX PHY, IEEE 802.3z
compliant 1000 BASE-T PHY, serial EEPROM
interface, expansion ROM interface and LED
drivers.
The IP1000A LF supports features for use in
“Green PCs” or systems where control over
system power consumption is desired. The
IP1000A LF supports several power down states,
and the ability to issue a system “wake event” via
reception of unique, user defined Ethernet frames.
In addition, the IP1000A LF can assert a wake
event in response to changes in the Ethernet link
status.
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IP1000A LF-DS-R08
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PIN Diagram
IP1000A LF
Preliminary Data Sheet
DEVSELN
STOPN
PERRN
VCC1
SERRN
PAR
VSS2
VSS1
VCC2
CBE1N
AD15
AD14
AD13
AD12
AD11
AD10
VSS1
VCC1
VCC2
VSS2
AD9
AD8
CBE0N
AD7
AD6
VSS1
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
IP1000A LF
64 VSS1
63 PMEN
62 GNTN
61 RSTN
60 VDET
59 INTAN
58 AVCC
57 AVSS
56 TP_MDI3 -
55 TP_MDI3 +
54 AVSS
53 AVCC
52 AVSS
51 TP_MDI2 -
50 TP_MDI2 +
49 AVSS
48
HSDAC_
P
47 AVCCH
46 AVSS
45 CTRL_REGA
44 AVCC
43 AVSS
42 TP_MDI1 -
41 TP_MDI1 +
40 AVSS
39 AVCC
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July 5, 2005
IP1000A LF-DS-R08
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IP1000A LF
Preliminary Data Sheet
2.1.2.3 Echo Canceller
With the proprietary architecture, the adaptive digital echo canceller further reduces the residual echo not
removed by the hybrid, the reflection due to patch cord impedance mismatch and non-ideal cable
characteristics.
2.1.2.4 NEXT Canceller
When IP1000A LF is operated in 1000BASE-T mode, it uses 4 pairs of wires to transmit and receive data
at the same time. This results in a detrimental near-end crosstalk between adjacent pairs and
significantly impairs the receiver performance. An adaptive digital NEXT canceller is implemented in
IP1000A LF to mitigate this effect.
2.1.2.5 Baseline Wander Canceller
IP1000A LF implements a digital adaptive baseline wander cancellation circuit to compensate DC shifts,
which are result of the DC loss from the transformer.
2.1.2.6 Feed-Forward Equalizer (FFE) and Decision-Feedback Equalizer (DFE)
The FFE and DFE of IP1000A LF are designed to remove inter-symbol interference. These fully adaptive
filters can track the inherently time-variant channel environment.
2.1.2.7 Digital Timing Recovery
IP1000A LF adopts a digital timing recovery scheme to accurately acquire the timing information at the
receiver side. This advanced digital timing recovery block reduces both long-term and short-term
frequency jitter to achieve as low bit error rate as possible. The maximum frequency offset it can track far
exceeds the requirement of the IEEE standard.
2.1.2.8 Decoder
The IP1000A LF implements different decoders for 1000BASE-T, 100BASE-TX, and 10BASE-T
respectively.
2.1.3 Transmit Function
2.1.3.1 Digital to Analog Converter (DAC)
The IP1000A LF incorporates a hightly integrated DAC to transmit Normal Link Pulse (NLP), Fast Link
Pulse (FLP), Manchester coded symbols, MLT3 waveform, or partial response PAM5 signals.
2.1.3.2 Encoder
The IP1000A LF implements different encoders for 1000BASE-T, 100BASE-TX, and 10BASE-T
respectively.
2.1.4 Link Function
2.1.4.1 Medium Dependent Interface (MDI)
The IP1000A LF transmits and receives data with all four pairs of wires in 1000BASE-T mode. If the
IP1000A LF is operated in 100BASE-TX or 10BASE-T mode, only one pair is responsible for transmitting
and the other for receiving data.
2.1.4.2 Automatic MDI/MDI-X Crossover and Pair Polarity Correction
The IP1000A LF is able to correct pair polarity errors in all modes. The automatic crossover function will
adjust MDI/MDI-X crossover condition for proper operation. In addition, the IP1000A LF can also correct
two types of abnormal cable configuration not compliant with the IEEE 802.3ab standard. This function
can be turned off by setting PHY register 20.2 to “0”.
Copyright © 2005, IC Plus Corp.
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July 5, 2005
IP1000A LF-DS-R08
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