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PDF PCA9665 Data sheet ( Hoja de datos )
| Número de pieza | PCA9665 | |
| Descripción | Fm parallel bus to I2C-bus controller | |
| Fabricantes | NXP Semiconductors | |
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PCA9665
Fm+ parallel bus to I2C-bus controller
Rev. 02 — 7 December 2006
Product data sheet
1. General description
The PCA9665 serves as an interface between most standard parallel-bus
microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus
system to communicate bidirectionally with the I2C-bus. The PCA9665 can operate as a
master or a slave and can be a transmitter or receiver. Communication with the I2C-bus is
carried out on a Byte or Buffered mode using interrupt or polled handshake. The
PCA9665 controls all the I2C-bus specific sequences, protocol, arbitration and timing with
no external timing element required.
The PCA9665 has the same footprint as the PCA9564 with additional features:
• 1 MHz transmission speeds
• Up to 25 mA drive capability on SCL/SDA
• 68-byte buffer
• I2C-bus General Call
• Software reset on the parallel bus
2. Features
I Parallel-bus to I2C-bus protocol converter and interface
I Both master and slave functions
I Multi-master capability
I Internal oscillator trimmed to 15 % accuracy reduces external components
I 1 Mbit/s and up to 25 mA SCL/SDA IOL (Fast-mode Plus (Fm+)) capability
I I2C-bus General Call capability
I Software reset on parallel bus
I 68-byte data buffer
I Operating supply voltage: 2.3 V to 3.6 V
I 5 V tolerant I/Os
I Standard-mode and Fast-mode I2C-bus capable and compatible with SMBus
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Packages offered: DIP20, SO20, TSSOP20, HVQFN20
1 page  
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PCA9665
Fm+ parallel bus to I2C-bus controller
6.2 Pin description
Table 2. Pin description
Symbol Pin
Type
DIP20,
HVQFN20
SO20,
TSSOP20
D0 1
18 I/O
D1 2
19 I/O
D2 3
20 I/O
D3 4
1 I/O
D4 5
2 I/O
D5 6
3 I/O
D6 7
4 I/O
D7 8
5 I/O
i.c. 9
6-
VSS 10
WR 11
7[1] power
8I
RD 12 9 I
CE 13
10 I
A0 14
A1 15
INT 16
RESET 17
SCL 18
SDA 19
VDD
20
11 I
12 I
13 O
14 I
15 I/O
16 I/O
17 power
Description
Data bus: Bidirectional 3-state data bus used to
transfer commands, data and status between the bus
controller and the CPU. D0 is the least significant bit.
internally connected: must be left floating (pulled
LOW internally)
Supply ground
Write strobe: When LOW and CE is also LOW, the
content of the data bus is loaded into the addressed
register. Data are latched on the rising edge of either
WR or CE.
Read strobe: When LOW and CE is also LOW,
causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on
the falling edge of RD.
Chip Enable: Active LOW input signal. When LOW,
data transfers between the CPU and the bus
controller are enabled on D0 to D7 as controlled by
the WR, RD and A0 to A1 inputs. When HIGH,
places the D0 to D7 lines in the 3-state condition.
Data are written into the addressed register on rising
edge of either CE or WR.
Address inputs: Selects the bus controller’s internal
registers and ports for read/write operations.
Interrupt request: Active LOW, open-drain, output.
This pin requires a pull-up device.
Reset: Active LOW input. A LOW level clears internal
registers and resets the I2C-bus state machine.
I2C-bus serial clock input/output (open-drain).
This pin requires a pull-up device.
I2C-bus serial data input/output (open-drain). This pin
requires a pull-up device.
Power supply: 2.3 V to 3.6 V
[1] HVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
PCA9665_2
Product data sheet
Rev. 02 — 7 December 2006
© NXP B.V. 2006. All rights reserved.
5 of 91
5 Page 
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PCA9665
Fm+ parallel bus to I2C-bus controller
Table 12. I2CCON - Control register (A1 = 1, A0 = 1) bit description …continued
Bit Symbol Description
5 STA
The START flag.
STA = 1: When the STA bit is set to enter a master mode, the bus controller
hardware checks the status of the I2C-bus and generates a START condition if the
bus is free. If the bus is not free, then the bus controller waits for a STOP condition
(which will free the bus) and generates a START condition after the minimum
buffer time (tBUF) has elapsed.
If STA is set while the bus controller is already in a master mode and one or more
bytes are transmitted or received, the bus controller transmits a repeated START
condition. STA may be set at any time. STA may also be set when the bus
controller is an addressed slave. A START condition will then be generated after a
STOP condition and the minimum buffer time (tBUF) has elapsed.
STA = 0: When the STA bit is reset, no START condition or repeated START
condition will be generated.
4 STO The STOP flag.
STO = 1: When the STO bit is set while the bus controller is in a master mode, a
STOP condition is transmitted on the I2C-bus. When a STOP condition is detected
on the bus, the hardware clears the STO flag.
If the STA and STO bits are both set, then a STOP condition is transmitted on the
I2C-bus, if the PCA9665 is in a master mode. the bus controller then transmits a
START condition after the minimum buffer time (tBUF) has elapsed.
STO = 0 : When the STO bit is reset, no STOP condition will be generated.
3 SI
The Serial Interrupt flag.
SI = 1: When the SI flag is set, and, if the ENSIO bit is also set, a serial interrupt is
requested. SI is set by hardware when one of 29 of the 30 possible states of the
bus controller states is entered. The only state that does not cause SI to be set is
state F8h, which indicates that no relevant state information is available.
While SI is set, the LOW period of the serial clock on the SCL line is stretched,
and the serial transfer is suspended. A HIGH level on the SCL line is unaffected
by the serial interrupt flag. SI is automatically cleared when the I2CCON register
is written. The SI bit cannot be set by the user.
SI = 0: When the SI flag is reset, no serial interrupt is requested, and there is no
stretching of the serial clock on the SCL line.
2:1 -
Reserved. When I2CCON is read, zeroes are read. Must be written with zeroes.
0 MODE The Mode flag.
MODE = 0; Byte mode. See Section 8.1.1 “Byte mode” for more detail.
MODE = 1; buffered mode. See Section 8.1.2 “Buffered mode” for more detail.
Remark: ENSIO bit value must be changed only when the I2C-bus is idle.
7.3.1.5 The indirect data field access register, INDIRECT (A1 = 1, A0 = 0)
The registers in the indirect address space can be accessed using the INDIRECT data
field. Before writing or reading such a register, the INDPTR register should be written with
the address of the indirect register that needs to be accessed. Once the INDPTR register
contains the appropriate value, reads and writes to the INDIRECT data field will actually
read and write the selected indirect register.
PCA9665_2
Product data sheet
Rev. 02 — 7 December 2006
© NXP B.V. 2006. All rights reserved.
11 of 91
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