PDF CS2100-CP Data sheet ( Hoja de datos )

Número de pieza	CS2100-CP
Descripción	Fractional-N Clock Multiplier
Fabricantes	Cirrus Logic
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No Preview Available ! www.DataSheet4U.com CS2100-CP Fractional-N Clock Multiplier Features Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source Highly Accurate PLL Multiplication Factor – Maximum Error Less Than 1 PPM in High- Resolution Mode I²C® / SPI™ Control Port Configurable Auxiliary Output Flexible Sourcing of Reference Clock – External Oscillator or Clock Source – Supports Inexpensive Local Crystal Minimal Board Space Required – No External Analog Loop-filter Components General Description The CS2100-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2100-CP is based on a hybrid ana- log-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an exter- nal noisy synchronization clock at frequencies as low as 50 Hz. The CS2100-CP supports both I²C and SPI for full software control. The CS2100-CP is available in a 10-pin MSOP pack- age in Commercial (-10°C to +70°C) grade. Customer development kits are also available for device evalua- tion. Please see “Ordering Information” on page 32 for complete details. I²C/SPI Software Control I²C / SPI 3.3 V Timing Reference Frequency Reference PLL Output Lock Indicator Auxiliary Output 8 MHz to 75 MHz Low-Jitter Timing Reference 50 Hz to 30 MHz Frequency Reference Fractional-N Frequency Synthesizer Output to Input Clock Ratio N Digital PLL & Fractional N Logic 6 to 75 MHz PLL Output Preliminary Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) JUN '08 DS840PP1 1 page www.DataSheet4U.com 2. TYPICAL CONNECTION DIAGRAM CS2100-CP Notes: 1. Resistors required for I2C operation. Note1 2 kΩ 2 kΩ System MicroController Frequency Reference 1 or 2 0.1 µF 1 µF +3.3 V VD SCL/CCLK SDA/CDIN AD0/CS CS2100-CP CLK_IN CLK_OUT XTI/REF_CLK XTO AUX_OUT GND To circuitry which requires a low-jitter clock To other circuitry or Microcontroller Low-Jitter Timing Reference 1 N.C. x Crystal 40 pF 40 pF or 2 REF_CLK XTO XTI XTO DS840PP1 Figure 1. Typical Connection Diagram 5 5 Page www.DataSheet4U.com Delta-Sigma Fractional-N Frequency Synthesizer Timing Reference Clock Phase Comparator Internal Loop Filter Voltage Controlled Oscillator Fractional-N Divider Delta-Sigma Modulator N Digital PLL and Fractional-N Logic Digital Filter Frequency Reference Clock Frequency Comparator for Frac-N Generation Output to Input Ratio for Hybrid mode Figure 5. Hybrid Analog-Digital PLL CS2100-CP PLL Output DS840PP1 11 11 Page

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Número de pieza	Descripción	Fabricantes
CS2100-CP	Fractional-N Clock Multiplier	Cirrus Logic

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