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부품번호 | FAN2559 기능 |
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기능 | (FAN2558 / FAN2559) 180mA Low Voltage CMOS LDO | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 15 페이지수
www.DataSheet4U.com
www.fairchildsemi.com
FAN2558/FAN2559
180mA Low Voltage CMOS LDO
Features
• Fixed 1.0V, 1.2V, 1.3V, 1.5V, 1.8V, 2.5V, 3.3V, 3.5V, 3.6V,
3.8V and Adjustable Output
• Power Good Indicator with Open Drain Output
• 180mA Output Current
• 100µA Ground Current
• Cbypass for Low Noise Operation
• Fast Enable for CDMA Applications
• High Ripple Rejection
• Current Limit
• Thermal Shutdown
• Excellent Line and Load Regulation
• Requires Only 1µF Output Capacitor
• Stable with 0 to 300mΩ ESR
• TTL-level Compatible Enable Input
• Active Output Discharge
Applications
• Processor Power-up sequencing
• PDAs, Cell Phones
• Portable Electronic Equipment
• PCMCIA Vcc and Vpp regulation/switching
General Description
The FAN2558/9 low voltage CMOS LDOs feature fixed or
adjustable output voltage, 180mA load current, delayed
power good output (open drain) and 1% output accuracy
with excellent line and load regulation. An external bypass
capacitor provides ultra-low noise operation.
The FAN2558/9 low voltage LDOs incorporate both thermal
shutdown and short circuit protection. Output is stable with a
1µF, low ESR capacitor. The FAN2558/9 family is available
in 5-Lead SOT-23, 6-Lead SOT-23 and 2x2mm MLP-6
packages.
FAN2558: Fixed Output LDO with Power Good output
FAN2558ADJ: Adjustable Output LDO with Power Good
output
FAN2559: Fixed Output LDO with Power Good output,
Low Noise
Available standard output voltages are 1.0, 1.2V, 1.3V, 1.5V,
1.8V, 2.5V, 3.3V, 3.5V, 3.6V, and 3.8V. Custom output volt-
age options are also available.
Typical Application
47KΩ
RPG
VFIBN VOUT
SHDN
GND
CAP+
ECNAP- PG
C OUT
47KΩ
RPG
VFIBN VOUT
SHDN
GND ADJ
CAP+
ECNAP- PG
R1
R2
C OUT
47KΩ
RPG
VFIBN VOUT
SHDN
GND CBYP
CAP+
ECNAP- PG
C OUT
C BYP
FAN2558
FAN2558ADJ
FAN2559
REV. 1.0.4 3/15/04
www.DataSheet4U.com
FAN2558/FAN2559
PRODUCT SPECIFICATIONS
Electrical Characteristics
VIN = VIN min (note 5) to 5.5V, VEN = VIN, ILOAD = 100µA, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at 25°C.
Symbol
VOUT
VOUT(ADJ)
∆VOUT_LNR
∆VOUT_LDR
ISD
IGND
ILIM
TSD
VENL
VENH
IE
VPG
VPGL
IPG
Parameter
Conditions
Output Voltage Accuracy
(Note 3)
ILOAD = 100µA
Output Voltage Range
(Adjustable)
ILOAD = 100µA
Line Regulation
Load Regulation (Note 4)
Supply Current in Shutdown
Mode
VIN min < VIN < 5.5V
ILOAD = 0.1mA to 150mA
VEN < 0.4V
PG = No Connection
Ground Pin Current (Note 4)
Current Limit
Thermal Shutdown
Temperature
ILOAD = 0mA, VIN = 5.5V
ILOAD = 150mA, VIN = 5.5V
VOUT = 0V
Thermal Shutdown Hysteresis
Enable Input Low
Enable Input High
Enable Input Current
Low Threshold
High Threshold
PG Output Low Voltage
VIN = 5.5V, Shutdown
VIN = 5.5V, Enabled
VENL ≤ 0.4V, VIN = 5.5V
VENH ≥ 1.6V, VIN = 5.5V
% of VOUT PG ON
% of VOUT PG OFF
IPG_SINK = 100µA,
Fault Condition
PG Leakage Current
PG off, VPG =5.5V
Min.
-2
1
-0.3
260
1.6
89
Typ.
1
2.5
0.1
90
110
350
150
10
0.01
0.01
0.02
0.01
Max.
2
VIN
0.3
4
150
150
500
0.4
97
0.1
Units
%
V
%/V
%
µA
µA
mA
°C
°C
V
V
µA
%
%
V
µA
TEN Enable Response Time
TON Power "ON" Delay Time
DPG
VDROP-OUT
VFB_ADJ
PG Delay time
Dropout Voltage
(For Adjustable Output
Version)
Feedback Voltage
(For Adjustable Output
Version)
COUT = 1µF
CBYPASS = 10nF
COUT = 1µF
CBYPASS = 10nF
VENL ≥ 1.6V,
VIN = 0V to VOUT + 1V
VOUT > 2.7V and
ILOAD = 180mA
1
Note:
3. Guaranteed ±1% output voltage accuracy parts are available on customer request.
4. Measured at constant junction temperature using low duty cycle pulse testing.
5. VIN min = 2.7V or (VOUT + 1V), whichever is greater.
30 300 µS
300 500 µS
5 mS
400 mV
0.59 V
4 REV. 1.0.4 3/15/04
4페이지 www.DataSPhReOeDt4UUC.cToSmPECIFICATIONS
FAN2558/FAN2559
Control Functions
Enable Pin
Connecting 2V or greater to the Enable pin will enable the
output, while 0.4V or less will disable it while reducing the
quiescent current consumption to less than 1µA. If this shut-
down function is not needed, the pin can simply be con-
nected permanently to the VIN pin. Allowing this pin to float
will cause erratic operation.
Error Flag (Power Good)
Fault conditions such as input voltage dropout (low VIN),
overheating, or overloading (excessive output current), will
set an error flag. The PG pin which is an open-drain output,
will go LOW when VOUT is less than 95% or the specified
output voltage. When the voltage at VOUT is greater than
95% of the specified output voltage, the PG pin is HIGH. A
logic pull-up resistor of 47KΩ is recommended at this out-
put. The pin can be left disconnected if unused.
Thermal Protection
The FAN2558/FAN2559 is designed to supply high peak
output currents for brief periods, however sustained exces-
sive output load at high input - output voltage difference will
increase the device’s temperature and exceed maximum rat-
ings due to power dissipation. During output overload condi-
tions, when the die temperature exceeds the shutdown limit
temperature of 150°C, an onboard thermal protection will
disable the output until the temperature drops approximately
10°C below the limit, at which point the output is re-enabled.
During a thermal shutdown, the user may assert the power-
down function at the Enable pin, reducing power consump-
tion to a minimum.
Thermal Characteristics
The FAN2558/FAN2559 is designed to supply 180mA at the
specified output voltage with an operating die (junction)
temperature of up to 125°C. Once the power dissipation and
thermal resistance is known, the maximum junction tempera-
ture of the device can be calculated. While the power dissipa-
tion is calculated from known electrical parameters, the
actual thermal resistance depends on the thermal characteris-
tics of the SOT23-5 surface-mount package and the sur-
rounding PC board copper to which it is mounted.
The power dissipation is equal to the product of the input-to-
output voltage differential and the output current plus the
ground current multiplied by the input voltage,
or:
PD = (VIN – VOUT) × IOUT + VIN × IGND
The ground pin current IGND can be found in the charts
provided in the Electrical Characteristics section.
The relationship describing the thermal behavior of the
package is:
PD(max)
=
T----J---(-m----θa---xJ---A)---–----T----A--
where TJ(max) is the maximum allowable junction tempera-
ture of the die, which is 125°C, and TA is the ambient operat-
ing temperature. θJA is dependent on the surrounding PC
board layout and can be empirically obtained. While the θJC
(junction-to-case) of the SOT23-5 package is specified at
130°C /W, the θJA of the minimum PWB footprint will be at
least 235°C /W. This can be improved by providing a heat
sink of surrounding copper ground on the PWB. Depending
on the size of the copper area, the resulting θJA can range
from approximately 180°C /W for one square inch to nearly
130°C /W for 4 square inches. The addition of backside cop-
per with through-holes, stiffeners, and other enhancements
can also aid in reducing thermal resistance. The heat contrib-
uted by the dissipation of other devices located nearby must
be included in the design considerations. Once the limiting
parameters in these two relationships have been determined,
the design can be modified to ensure that the device remains
within specified operating conditions. If overload conditions
are not considered, it is possible for the device to enter a
thermal cycling loop, in which the circuit enters a shutdown
condition, cools, re-enables, and then again overheats and
shuts down repeatedly due to an unmanaged fault condition.
Adjustable Version
The FAN2558ADJ includes an input pin ADJ which allows
the user to select an output voltage ranging from 1V to near
VIN, using an external resistor divider. The voltage VADJ pre-
sented to the ADJ pin is fed to the onboard error amplifier
which adjusts the output voltage until VADJ is equal to the
onboard bandgap reference voltage of 1.00V(typ). The equa-
tion is:
VOUT = 0.59V × 1 + R-R----12
Since the bandgap reference voltage is trimmed, 1% initial
accuracy can be achieved. The total value of the resistor
chain should not exceed 250KOhm total to keep the error
amplifier biased during no-load conditions. Programming
output voltages very near VIN need to allow for the magni-
tude and variation of the dropout voltage VDO over load, sup-
ply, and temperature variations. Note that the low-leakage
FET input to the CMOS error amplifier induces no bias
current error to the calculation.
REV. 1.0.4 3/15/04
7
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부품번호 | 상세설명 및 기능 | 제조사 |
FAN2558 | (FAN2558 / FAN2559) 180mA Low Voltage CMOS LDO | Fairchild Semiconductor |
FAN2559 | (FAN2558 / FAN2559) 180mA Low Voltage CMOS LDO | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |