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PDF A4447 Data sheet ( Hoja de datos )
| Número de pieza | A4447 | |
| Descripción | High Voltage Step Down Regulator | |
| Fabricantes | Allegro Micro Systems | |
| Logotipo |  |
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A4447
High Voltage Step Down Regulator
Features and Benefits
▪ Wide input voltage range: 8 to 50 V
▪ Integrated low RDS(on) DMOS switch
▪ 2 A continuous output current
▪ Adjustable fixed off-time
▪ Highly efficient
▪ Adjustable output: 0.8 to 24 V
▪ Small package with exposed thermal pad
Package: 8 pin SOIC with exposed thermal
pad (suffix LJ)
Description
The A4447 is a 2A, high efficiency general-purpose buck
regulator designed for a wide variety of applications.The output
voltage is adjustable from 0.8 to 24 V, based on a resistor divider
and the 0.8 V ± 2 % reference. External components include
an external clamping diode, inductor, and filter capacitor.
The off-time is determined by an external resistor to ground.
It operates in both continuous and discontinuous modes to
maintain light load regulation. An internal blanking circuit is
used to filter out transients due to the reverse recovery of the
external clamp diode. Typical blanking time is 200 ns.
This new device is ideal for various end products including
applications with 8 to 50 V input voltage range and require up
to 2 A output current, such as uninterruptible power supplies,
point of sale (POS) applications, and industrial applications
with 24 or 36 V bus.
Applications include:
▪ Printer power supplies
▪ Office automation equipment
▪ POS thermal, laser, photo, and inkjet printers
▪ Tape drives
▪ Industrial applications
Approximate Scale 1:1
Typical Application
+42 V
CBOOT
0.01 μF
CIN2
BOOT
VIN
ENB LX
A4447
D1
L1
RTSET
54 k7
TSET
GND
VBIAS
FB
A R3 required when CBYP connected
R1
2.87 k7
R3 A
10 k7
R2
910 7
CBYP
0.22 μF
CIN1
0.22 μF
VOUT
3.3 V
2A
ESR
COUT
220 μF
25 V
Efficiency vs. Output Current
90
85
80
75
70
65
60
0
5
3.3
1.8
1.5
VOUT (V)
500 1000
IOUT (mA)
1500
2000
A4447-DS, Rev. 2
Data is for reference only. Efficiency data from circuit shown in left panel.
1 page  
A4447
High Voltage Step Down Regulator
Functional Description
The A4447 is a fixed off-time, current mode controlled, buck
regulator. The regulator requires an external clamping diode,
inductor, and filter capacitor. It operates in both continuous and
discontinuous modes. An internal blanking circuit is used to filter
out transients resulting from the reverse recovery of the external
clamp diode. Typical blanking time is 200 ns.
The value of a resistor between the TSET and GND determines
the fixed off-time (see graph in the tOFF section).
VOUT. The output voltage is adjustable from 0.8 to 24 V, set by an
external resistor divider. The voltage can be calculated with the
following formula:
VOUT = VFB × (1 + R1/R2)
(1)
Light Load Regulation. To maintain voltage regulation during
light load conditions, the switching regulator enters a cycle-skip-
ping mode. As the output current decreases, there remains some
energy that is stored during the power switch minimum on-time.
In order to prevent the output voltage from rising, the regulator
skips cycles once it reaches the minimum on-time, effectively
making the off-time larger.
Soft Start. An internal ramp generator and counter allow the out-
put to slowly ramp up. This limits the maximum demand on the
external power supply by controlling the inrush current required
to charge the external capacitor and any DC load at startup.
Internally, the ramp is set to 10 ms nominal rise time. During soft
start, current limit is 2.2 A minimum.
The following conditions are required to trigger a soft start:
• VIN > 6 V
• ENB pin input falling edge
• Reset of a TSD (thermal shut down) event
VBIAS. To improve overall system efficiency, the regulator output,
VOUT, is connected to the VBIAS input to supply the operating
bias current during normal operating conditions. During startup
the circuitry is run off of the VIN supply. VBIAS should be con-
nected to VOUT when the VOUT target level is between 3.3 and
5 V. If the output voltage is less than 3.3 V, then the A4447 can
operate with an internal supply and pay a penalty in efficiency,
as the bias current will come from the high voltage supply, VIN.
VBIAS can also be supplied with an external voltage source. No
power-up sequencing is required for normal operation.
ON/OFF Control. The ENB pin is externally pulled to ground
to enable the device and begin the soft start sequence. When the
ENB is open circuited, the switcher is disabled and the output
decays to 0 V.
Protection. The buck switch will be disabled under one or more
of the following fault conditions:
• VIN < 6 V
• ENB pin = open circuit
• TSD fault
When the device comes out of a TSD fault, it will go into a soft
start to limit inrush current.
tOFF. The value of a resistor between the TSET pin and ground
determines the fixed off-time. The formula to calculate tOFF (μs)
is:
tOFF
=
RTSET
⎛
⎜
⎝
1–100.0.23××1V0B9IAS⎟⎠⎞
,
(2)
where RTSET (kΩ) is the value of the resistor. If the VBIAS pin is
left open, use VBIAS = 0 in equation 2. Results are shown in the
following graph:
Off-Time Setting versus Resistor Value
200
180
160
140
120 VBIAS = 5 V
100 VBIAS = 3.3 V
80
60
40
20
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
tOFF (µs)
The RTSET resistor should be not smaller than 7.65 kΩ ±2% to
prevent very short off-times from violating the minimum on-time
of the switcher.
Shorted Load. If the voltage on the FB pin falls below 0.4 V, the
regulator will invoke a 0.85 A typical overcurrent limit to handle
the shorted load condition at the regulator output. For low output
voltages at power up and in the case of a shorted output, the off-
time is extended to prevent loss of control of the current limit due
to the minimum on-time of the switcher.
The extension of the off-time is based on the value of the TSET
multiplier and the FB voltage, as shown in the following table:
VFB (V)
< 0.16
< 0.32
< 0.5
> 0.5
TSET Multiplier
8 × tOFF
4 × tOFF
2 × tOFF
tOFF
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page 
A4447
High Voltage Step Down Regulator
Package LJ, 8 Pin SOIC
4.90 ±0.10
8
2.41 NOM
A
B
12
3.30 NOM
3.90 ±0.10 6.00 ±0.20
8X
0.10 C
0.51
0.31
1.27 BSC
Branded Face
SEATING
PLANE
C
1.70 MAX
0.15
0.00
8°
0°
0.25
0.17
1.04 REF
0.65
8
1.75
1.27
2.41 5.60
1.27
0.40
0.25 BSC
SEATING PLANE
GAUGE PLANE
12
3.30
C PCB Layout Reference View
For Reference Only; not for tooling use (reference MS-012BA)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface); dimensions may vary with device
C Reference land pattern layout (reference IPC7351
SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Pin Out Diagram
BOOT 1
8 VIN
ENB 2
7 LX
Pad
TSET 3
6 VBIAS
GND 4
5 FB
Terminal List Table
Number
1
2
3
4
5
6
7
8
Name
BOOT
ENB
TSET
GND
FB
VBIAS
LX
VIN
Description
Gate drive boost node
On/off control; logic input
Off-time setting
Ground
Feedback for adjustable regulator
Bias supply input
Buck switching node
Supply input
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet A4447.PDF ] | |
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