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PDF AKD4648-C Data sheet ( Hoja de datos )
| Número de pieza | AKD4648-C | |
| Descripción | Stereo CODEC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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[AKD4648-C]
AKD4648-C
Evaluation board Rev.1 for AK4648
GENERAL DESCRIPTION
AKD4648 is an evaluation board for the AK4648, stereo CODEC with MIC/HP/SPK amplifier. The
AKD4648 can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D →
D/A). The AKD4648 also has the digital audio interface and can achieve the interface with digital audio
systems via opt-connector.
Ordering guide
AKD4648 --- Evaluation board for AK4648
(Cable, USB interface board for connecting with USB port, and control software are
packed with this. This control software does not support Windows NT.)
FUNCTION
• DIT/DIR with optical input/output
• 10pin Header for digital audio interface
• 10pin Header for serial control mode
VCC
Regulator
3.3 V
TVDD
MIC
MIN
LINE
IN
HP
LINE
OUT
SPK
HVDD AVDD DVDD TVDD
AK4648
AGND
D3V
AK4115
PORT1
DIR Opt In
DIT Opt out
PORT2
DSP
10pin Header
PORT3
Control Data
10pin Header
PORT4
Figure 1. AKD4648-C Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual
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[AKD4648-C]
www.DataSheet4U.com
(2) External Master Mode
(2-1) Evaluation of A/D using DIT of AK4115
PORT2 (DIT) and X1 (X’tal) are used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP).
In Master Mode, BICK and LRCK of AK4648 should be input to AK4115. Please refer to Table2 on page 11.
The jumper pins should be set as follows.
JP14
4115_MCKI
JP15
DIR_MCLK
JP16
BICK
JP17
LRCK
JP19
DIR_SEL
Slave Master
(2-2) Evaluation of D/A using DIR of AK4115
PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP).
In Master Mode, BICK and LRCK of AK4648 should be input to AK4115. Please refer to Table2 on page 11.
The jumper pins should be set as follows.
JP14
4115_MCKI
JP15
DIR_MCLK
JP16
BICK
JP17
LRCK
JP19
DIR_SEL
JP21
SDTI
Slave Master
DIR ADC
(2-3) Evaluation of Loop-back using AK4115
X1 (X’tal) is used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP).
The jumper pins should be set as follows.
JP14
4115_MCKI
JP15
DIR_MCLK
JP16
BICK
JP17
LRCK
JP19
DIR_SEL
Slave Master
JP21
SDTI
DIR ADC
(2-4) All interface signals are fed externally
PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT).
The jumper pins should be set as follows.
JP20
SDTO-IN
JP15
DIR_MCLK
JP16
BICK
JP17
LRCK
JP19
DIR_SEL
Slave Master
JP21
SDTI
DIR ADC
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Other jumper pins set up
[JP1] (GND) : Analog ground and Digital ground.
SHORT : Common. (The connector “DGND” can be open.)
OPEN :
Separated. <Default>
[JP2] : Selection of RIN3 path or PLL Mode.
RIN3 :
RIN3 path.
VCOC :
PLL Mode. <Default>
[JP4] (LIN1) : Selection of using MIC-power supply for LIN1.
SHORT : MIC-power is supplied.
OPEN :
MIC-power is not supplied. <Default>
[JP7] (RIN1) : Selection of using MIC-power supply for RIN1.
SHORT : MIC-power is supplied.
OPEN :
MIC-power is not supplied. <Default>
[JP8] (LIN2) : Selection of using MIC-power supply for LIN2.
SHORT : MIC-power is supplied.
OPEN :
MIC-power is not supplied. <Default>
[JP9] (RIN2) : Selection of using MIC-power supply for RIN2.
SHORT : MIC-power is supplied.
OPEN :
MIC-power is not supplied. <Default>
[JP12] : Selection of LIN3 path or MIN path.
SHORT : LIN3 path.
OPEN:
MIN path. <Default>
[JP14] (4114_MCKI) : AK4115 Clock Source.
OPEN :
X’tal of AK4115 is used. <Default>
SHORT : MCKO of AK4648 (X’tal oscillator should be removed from X1).
[JP18] (Signal V_select) : Selection of power supply for logic(U4).
D3V :
It is supplied from D3V. <Default>
TVDD :
It is supplied from TVDD.
[JP20] (SDTO_IN) : SDTO of PORT3.
SHORT : It supply SDTO to PORT3.
OPEN :
It does not supply SDTO to PORT3. <Default>
[AKD4648-C]
<KM088701>
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2007/04
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