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PDF LPC3130 Data sheet ( Hoja de datos )
| Número de pieza | LPC3130 | |
| Descripción | (LPC3130 / LPC3131) Lowest Cost ARM9 | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LPC3130 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LPC3130/3131
Low-cost, low-power ARM926EJ-S MCUs with high-speed
USB 2.0 OTG, SD/MMC, and NAND flash controller
Rev. 1.01 — 21 May 2009
Preliminary data sheet
1. General description
The NXP LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB
2.0 On-The-Go (OTG), up to 192 KB SRAM, NAND flash controller, flexible external bus
interface, four channel 10-bit ADC, and a myriad of serial and parallel interfaces in a
single chip targeted at consumer, industrial, medical, and communication markets. To
optimize system power consumption, the LPC3130/3131 have multiple power domains
and a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and
scaling.
2. Features
2.1 Key features
CPU platform
180 MHz, 32-bit ARM926EJ-S
16 kB D-cache and 16 kB I-cache
Memory Management Unit (MMU)
Internal memory
96 kB (LPC3130) or 192 kB (LPC3131) embedded SRAM
External memory interface
NAND flash controller with 8-bit ECC
8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM
Communication and connectivity
High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY
Two I2S-bus interfaces
Integrated master/slave SPI
Two master/slave I2C-bus interfaces
Fast UART
Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA
Four-channel 10-bit ADC
Integrated 4/8/16-bit 6800/8080 compatible LCD interface
System functions
Dynamic clock gating and scaling
Multiple power domains
Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB
DMA controller
Four 32-bit timers
1 page  
NXP Semiconductors
www.DataSheet4U.com
LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
Table 3. Pin allocation table …continued
Pin Symbol
Pin Symbol
Row E
1 EBI_D_3
2 EBI_D_4
5 VDDE_IOA
6 mNAND_RYBN0
9 VSSA12
10 VDDA12
13 I2C_SCL1
14 I2STX_BCK1
Row F
1 EBI_D_2
2 EBI_D_1
5 VDDE_IOA
10 SCAN_TDO
13 I2SRX_WS1
14 I2SRX_BCK1
Row G
1 EBI_NCAS_BLOUT_0 2 EBI_D_0
5 VDDE_IOA
10 I2STX_WS1
13 SYSCLK_O
14 I2SRX_DATA1
Row H
1 EBI_DQM_0_NOE
2 EBI_NRAS_BLOUT_1
5 VDDE_IOA
10 GPIO12
13 GPIO11
14 RSTIN_N
Row J
1 NAND_NCS_0
2 EBI_NWE
5 USB_RREF
10 GPIO1
13 GPIO15
14 GPIO14
Row K
1 NAND_NCS_2
2 NAND_NCS_3
5 mLCD_DB_12
6 mLCD_DB_6
9 TDI
10 GPIO0
13 GPIO20
14 GPIO18
Row L
1 USB_VDDA12_PLL
2 USB_VBUS
5 mLCD_DB_9
6 VSSI
9 VSSE_IOC
10 VDDE_IOC
13 VSSE_IOC
14 GPIO2
Row M
1 USB_ID
2 USB_VDDA33_DRV
5 VDDE_IOB
6 VSSE_IOB
9 VDDE_IOB
10 I2SRX_DATA0
13 mI2STX_DATA0
14 TCK
Row N
1 USB_GNDA
2 USB_DM
5 mLCD_DB_8
6 mLCD_DB_2
9 mLCD_RW_WR
10 I2SRX_BCK0
13 mUART_CTS_N
14 mI2STX_CLK0
Pin Symbol
3 EBI_D_14
7 mNAND_RYBN1
11 ARM_TDO
--
3 EBI_D_15
11 BUF_TRST_N
--
3 EBI_D_12
11 VSSE_IOC
--
3 VDDI
11 GPIO19
--
3 NAND_NCS_1
11 GPIO16
--
3 VSSE_IOA
7 mLCD_DB_10
11 VDDE_IOC
--
3 USB_VSSA_TERM
7 VDDI
11 VSSI
--
3 VSSE_IOB
7 VDDE_IOB
11 mI2STX_WS0
--
3 mLCD_DB_15
7 mLCD_DB_4
11 JTAGSEL
--
LPC3130_3131_1
Preliminary data sheet
Rev. 1.01 — 21 May 2009
Pin Symbol
4 VSSE_IOA
8 VDDE_IOC
12 I2C_SDA1
--
4 VSSE_IOA
12 I2STX_DATA1
--
4 VSSI
12 VDDE_IOC
--
4 VSSE_IOA
12 CLK_256FS_O
--
4 CLOCK_OUT
12 GPIO13
--
4 USB_VSSA_REF
8 mLCD_CSB
12 GPIO17
--
4 VDDE_IOB
8 mLCD_E_RD
12 VDDI
--
4 VSSE_IOB
8 VSSE_IOB
12 mI2STX_BCK0
--
4 mLCD_DB_11
8 mLCD_DB_0
12 UART_TXD
--
© NXP B.V. 2009. All rights reserved.
5 of 68
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LPC3130/3131
Low-cost, low-power ARM926EJ-S microcontrollers
Table 4. Pin description
Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
Pin name
BGA
Ball
Digital
I/O
level
[1]
Application
function
Pin
state
after
reset
Cell
Type [2]
Description
External Bus Interface (NAND flash controller)
EBI_A_0_ALE[3]
B3 SUP4 DO
O DIO4 EBI Address Latch Enable
EBI_A_1_CLE[3]
A2 SUP4 DO
O DIO4 EBI Command Latch Enable
EBI_D_0[3]
G2 SUP4 DIO
I
DIO4
EBI Data I/O 0
EBI_D_1[3]
F2 SUP4 DIO
I
DIO4
EBI Data I/O 1
EBI_D_2[3]
F1 SUP4 DIO
I
DIO4
EBI Data I/O 2
EBI_D_3[3]
E1 SUP4 DIO
I
DIO4
EBI Data I/O 3
EBI_D_4[3]
E2 SUP4 DIO
I
DIO4
EBI Data I/O 4
EBI_D_5[3]
D1 SUP4 DIO
I
DIO4
EBI Data I/O 5
EBI_D_6[3]
D2 SUP4 DIO
I
DIO4
EBI Data I/O 6
EBI_D_7[3]
C1 SUP4 DIO
I
DIO4
EBI Data I/O 7
EBI_D_8[3]
B1 SUP4 DIO
I
DIO4
EBI Data I/O 8
EBI_D_9[3]
A3 SUP4 DIO
I
DIO4
EBI Data I/O 9
EBI_D_10[3]
A1 SUP4 DIO
I
DIO4
EBI Data I/O 10
EBI_D_11[3]
C2 SUP4 DIO
I
DIO4
EBI Data I/O 11
EBI_D_12[3]
G3 SUP4 DIO
I
DIO4
EBI Data I/O 12
EBI_D_13[3]
D3 SUP4 DIO
I
DIO4
EBI Data I/O 13
EBI_D_14[3]
E3 SUP4 DIO
I
DIO4
EBI Data I/O 14
EBI_D_15[3]
F3 SUP4 DIO
I
DIO4
EBI Data I/O 15
EBI_DQM_0_NOE[3]
H1 SUP4 DO
O DIO4 NAND Read Enable (active LOW)
EBI_NWE[3]
J2 SUP4 DO
O DIO4 NAND Write Enable (active LOW)
NAND_NCS_0[3]
J1 SUP4 DO
O DIO4 NAND Chip Enable 0
NAND_NCS_1[3]
J3 SUP4 DO
O DIO4 NAND Chip Enable 1
NAND_NCS_2[3]
K1 SUP4 DO
O DIO4 NAND Chip Enable 2
NAND_NCS_3[3]
K2 SUP4 DO
O DIO4 NAND Chip Enable 3
mNAND_RYBN0[3]
E6 SUP4 DI
I
DIO4
NAND Ready/Busy 0
mNAND_RYBN1[3]
E7 SUP4 DI
I
DIO4
NAND Ready/Busy 1
mNAND_RYBN2[3]
B4 SUP4 DI
I
DIO4
NAND Ready/Busy 2
mNAND_RYBN3[3]
D4 SUP4 DI
I
DIO4
NAND Ready/Busy 3
EBI_NCAS_BLOUT_0[3] G1 SUP4 DO
O DIO4 EBI Lower lane byte select (7:0)
EBI_NRAS_BLOUT_1[3] H2 SUP4 DO
O DIO4 EBI Upper lane byte select (15:8)
Pulse Width Modulation module
PWM_DATA[3]
B9 SUP3 DO / GPIO O
DIO1
PWM Output
[1] Digital I/O levels are explained in Table 5.
[2] Cell types are explained in Table 6.
[3] Pin can be configured as GPIO pin in the IOCONFIG block.
[4] The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if these balls are not required for
UART flow control, they can also be selected to be used for an alternative function: SPI chip select signals (SPI_CS_OUT1 and
SPI_CS_OUT2)
LPC3130_3131_1
Preliminary data sheet
Rev. 1.01 — 21 May 2009
© NXP B.V. 2009. All rights reserved.
11 of 68
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LPC3130.PDF ] | |
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