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AT91CAP9SC250A 데이터시트 PDF




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부품번호 AT91CAP9SC250A 기능
기능 (AT91CAP9SC250A / AT91CAP9SC500A) Customizable Microcontroller Processor
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AT91CAP9SC250A 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Features
Incorporates the ARM926EJ-SARM® Thumb® Processor
– DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration
– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 220 MIPS at 200 MHz
– Memory Management Unit
– EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support
Additional Embedded Memories
– One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed
– One 32 Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed
External Bus Interface (EBI)
– EBI Supports Mobile DDR, SDRAM, Low Power SDRAM, Static Memory,
Synchronous CellularRAM, ECC-enabled NAND Flash and CompactFlash®
Metal Programmable (MP) Block
– 500,000 Gates/250,000 Gates Metal Programmable Logic (through 5 Metal Layers)
for AT91CAP9SC500A/AT91CAP9SC250A Respectively
– Ten 512 x 36-bit Dual Port RAMs
– Eight 512 x 72-bit Single Port RAMs
– High Connectivity for Up to Three AHB Masters and Four AHB Slaves
– Up to Seven AIC Interrupt Inputs
– Up to Four DMA Hardware Handshake Interfaces
– Delay Lines for Double Data Rate Interface
– UTMI+ Full Connection
– Up to 77 Dedicated I/Os
LCD Controller
– Supports Passive or Active Displays
– Up to 24 Bits per Pixel in TFT Mode, Up to 16 Bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Wider
Screen Buffers
Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
USB 2.0 Full Speed (12 Mbits per second) OHCI Host Double Port
– Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
USB 2.0 High Speed (480 Mbits per second) Device Port
– On-chip Transceiver, 4 Kbyte Configurable Integrated DPRAM
– Integrated FIFOs and Dedicated DMA Channels
– Integrated UTMI+ Physical Interface
Ethernet MAC 10/100 Base T
– Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
Multi-Layer Bus Matrix
– Twelve 32-bit-layer Matrix, Allowing a Maximum of 38.4 Gbps of On-chip Bus
Bandwidth at Maximum 100 MHz System Clock Speed
– Boot Mode Select Option, Remap Command
Fully-featured System Controller, Including
– Reset Controller, Shutdown Controller
Customizable
Microcontroller
Processor
AT91CAP9SC500A
AT91CAP9SC250A
Summary
Preliminary
NOTE: This is a summary document.
The complete document is available
under NDA. Please contact an Atmel
Sales Representative.
www.atmel.com/contacts/
6270AS–CAP–10-Jan-08




AT91CAP9SC250A pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
1. Description
The AT91CAP9SC500A/AT91CAP9SC250A family is based on the integration of an
ARM926EJ-S processor with fast ROM and SRAM memories, and a wide range of peripherals.
By providing up to 500K gates of metal programmable logic,
AT91CAP9SC500A/AT91CAP9SC250A is the ideal platform for creating custom designs.
The AT91CAP9SC500A/AT91CAP9SC250A embeds a USB High-speed Device, a 2-port USB
OHCI Host, an LCD Controller, a 4-channel DMA Controller, and one Image Sensor Interface. It
also integrates several standard peripherals, such as USART, SPI, TWI, Timer Counters, PWM
generators, Multimedia Card interface, and one CAN Controller.
The AT91CAP9SC500A/AT91CAP9SC250A is architectured on a 12-layer matrix, allowing a
maximum internal bandwidth of twelve 32-bit buses. It also features one external memory bus
(EBI) capable of interfacing with a wide range of memory devices.
The AT91CAP9SC500A/AT91CAP9SC250A is packaged in a 400-ball LFBGA RoHS-compliant
package. It can also be delivered in a 324-ball TFBGA RoHS-compliant package according to
the customer’s requirements.
4 AT91CAP9SC500A/AT91CAP9SC250A Preliminary
6270AS–CAP–10-Jan-08

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AT91CAP9SC250A 전자부품, 판매, 대치품
AT91CAP9SC500A/AT91CAP9SC250A Preliminary
www.DataSheet4U.com
Table 3-1. Signal Description List (Continued)
Signal Name
NTRST
TCK
TDI
TDO
TMS
JTAGSEL
RTCK
NRST
TST
BMS
DRXD
DTXD
IRQ0 - IRQ1
FIQ
PA0 - PA31
PB0 - PB31
PC0 - PC31
PD0 - PD31
DMARQ0-DMARQ3
D0 - D31
A0 - A25
NWAIT
NCS0 - NCS5
NWR0 - NWR3
NRD
NWE
NBS0 - NBS3
Function
Type
ICE and JTAG
Test Reset Signal
Input
Test Clock
Input
Test Data In
Input
Test Data Out
Output
Test Mode Select
Input
JTAG Selection
Input
Return Test Clock
Output
Reset/Test
Microcontroller Reset
I/O
Test Mode Select
Input
Boot Mode Select
Input
Debug Unit - DBGU
Debug Receive Data
Input
Debug Transmit Data
Output
Advanced Interrupt Controller - AIC
External Interrupt Inputs
Input
Fast Interrupt Input
Input
PIO Controller - PIOA - PIOB - PIOC - PIOD
Parallel IO Controller A
I/O
Parallel IO Controller B
I/O
Parallel IO Controller C
I/O
Parallel IO Controller D
I/O
Direct Memory Access Controller - DMA
DMA Requests
Input
External Bus Interface - EBI
Data Bus
I/O
Address Bus
Output
External Wait Signal
Input
Static Memory Controller - SMC
Chip Select Lines
Output
Write Signal
Output
Read Signal
Output
Write Enable
Output
Byte Mask Signal
Output
Active
Level
Low
Low
Low
Low
Low
Low
Low
Low
Comments
No pull-up resistor
No pull-up resistor
No pull-up resistor
No pull-up resistor
Pull-down resistor
Pull-up resistor
Pull-down resistor
Pull-up resistor
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
0 at reset
6270AS–CAP–10-Jan-08
7

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부품번호상세설명 및 기능제조사
AT91CAP9SC250A

(AT91CAP9SC250A / AT91CAP9SC500A) Customizable Microcontroller Processor

ATMEL Corporation
ATMEL Corporation

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