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PDF TSXPC603R Data sheet ( Hoja de datos )
| Número de pieza | TSXPC603R | |
| Descripción | PowerPC 603e RISC Microprocessor Family PID7t-603e | |
| Fabricantes | ATMEL Corporation | |
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Features
• Superscalar (3 Instructions per Clock Peak)
• Dual 16 KB Caches
• Selectable Bus Clock
• 32-bit Compatibility PowerPC Implementation
• On-chip Debug Support
• Nap, Doze and Sleep Power Saving Modes
• Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255
Features Specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 255
• 7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated)
• PD Typically = 3.5W (266 MHz), Full Operating Conditions
• Branch Folding
• 64-bit Data Bus (32-bit Data Bus Option)
• 4-Gbytes Direct Addressing Range
• Pipelined Single/Double Precision Float Unit
• IEEE 754 Compatible FPU
• IEEE P 1149-1 Test Mode (JTAG/C0P)
• fINT Max = 300 MHz
• fBUS Max = 75 MHz
• Compatible CMOS Input/TTL Output
Features Specific to Cerquad
• 5.6 SPECint95, 4 SPECfp95 and 200 MHz (Estimated)
• PD Typically = 2.5W (200 MHz), Full Operating Conditions
1. Description
The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a
low-power implementation of the Reduced Instruction Set Computer (RISC) micropro-
cessor PowerPC family. The 603R is pin-to-pin compatible with the PowerPC 603e
and 603P in a Cerquad package. The 603R implements 32-bit effective addresses,
integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.
The 603R is a low-power 2.5/3.3V design and provides four software controllable
power-saving modes. This device is a superscalar processor capable of issuing and
retiring as many as three instructions per clock. Instructions can be executed in any
order for increased performance, but, the 603R makes completion appear sequential.
It integrates five execution units and is able to execute five instructions in parallel.
The 603R provides independent on-chip, 16-Kbyte, four-way set-associative, physi-
cally addressed caches for instructions and data, as well as on-chip instructions, and
data Memory Management Units (MMUs). The MMUs contain 64-entry, two-way
set-associative, data and instruction translation look aside buffers that provide support
for demand-paged virtual memory address translation and variable-sized block trans-
lation. The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The
interface protocol allows multiple masters to compete for system resources through a
central external arbiter. The device supports single-beat and burst data transfers for
memory accesses, and supports memory-mapped I/Os.
PowerPC® 603e
RISC
Microprocessor
Family
PID7t-603e
TSPC603R
Rev. 5410B–HIREL–09/05
1 page  
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Figure 5-1. Functional Signal Groups
ADDRESS
ARBITRATION
BR
BG
ABB
ADDRESS
START
ADDRESS
BUS
TRANSFER
ATTRIBUTE
TS
A[0-31]
AP[0-3]
APE
TT[0-4]
TBST
TSIZ[0-2]
GBL
CI
WT
CSE[0-1]
TC[0-1]
ADDRESS
TERMINATION
CLOCKS
POWER SUPPLY
INDICATOR
AACK
ARTRY
SYSCLK
CLK_OUT
PLL_CFG[0-3]
VOLTDETGND
TSPC603R
11
11
11
DBG
DBWO
DBB
1 64
8
32 1
1
4
11
1
51
1
32
11
12
1 603r 2
2
21
2
1
1
1
1
5
DH[0-31], DL[0-31]
DP[0-7]
DPE
DBDIS
TA
DR TR Y
TEA
INT, SMI
MCP
CKSTP_IN, CKSTP_OUT
HRESET, SRESET
RSRV
QREQ, QACK
TBEN
TLBISYNC
TRST, TCK, TMS, TDI, TD0
1 LSSD_MODE
1
L1_TSTCLK, L2_TSTCLK
3
4
20
VDD
1 19
OVDD
40 GND
AVDD
1
DATA
ATTRIBUTION
DATA
TRANSFER
DATA
TERMINATION
INTERRUPTS
CHECKSTOPS
RESET
PROCESSOR
STATUS
JTAG/COP
INTERFACE
LSSD TEST
CONTROL
POWER SUPPLY
6. Detailed Specifications
This specification describes the specific requirements for the microprocessor TSPC603R, in
compliance with MIL-STD-883 class B or Atmel standard screening.
7. Applicable Documents
1. MIL-STD-883: Test methods and procedures for electronics
2. MIL-PRF-38535: General specifications for microcircuits
The microcircuits are in accordance with the applicable documents and as specified herein.
5410B–HIREL–09/05
5
5 Page 
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TSPC603R
• Functional units are clocked only when needed
• No software or hardware intervention required after mode is set
• Software/hardware and performance are transparent
Doze Mode
The doze mode disables most functional units but maintains cache coherency by enabling the
bus interface unit and snooping. A snoop hit will cause the 603R to enable the data cache, copy
the data back to the memory, disable the cache, and fully return to the doze state. In this mode:
• Most functional units are disabled
• Bus snooping and time base/decrementer are still enabled
• Dose mode sequence:
– Set doze bit (HID0[8) = 1)
– 603R enters doze mode after several processor clocks
• There are several methods for returning to full-power mode
– Assert INT, SMI, MCP or decrementer interrupts
– Assert hard reset or soft reset
• The Transition to full-power state takes no more than a few processor cycles
• Phase Locked Loop (PLL) running and locked to SYSCLK
Nap Mode
The nap mode disables the 603R but still maintains the phase locked loop (PLL) and the time
base/decrementer. The time base can be used to restore the 603R to full-on state after a pro-
grammed amount of time. Because bus snooping is disabled for nap and sleep modes, a
hardware handshake using the quiesce request (QREQ) and quiesce acknowledge (QACK) sig-
nals is required to maintain data coherency. The 603R will assert the QREQ signal to indicate
that it is ready to disable bus snooping. When the system has ensured that snooping is no
longer necessary, it will assert QACK and the 603R will enter the sleep or nap mode. In this
mode:
• The time base/decrementer is still enabled
• Most functional units are disabled (including bus snooping)
• All non-essential input receivers are disabled
• Nap mode sequence:
– Set nap bit (HID0[9] = 1)
– 603R asserts quiesce request (QREQ) signal
– System asserts quiesce acknowledge (QACK) signal
– 603R enters sleep mode after several processor clocks
• There are several methods for returning to full-power mode:
– Assert INT, SPI, MCP or decrementer interrupts
– Assert hard reset or soft reset
• Transition to full-power takes no more than a few processor cycles
• The PLL is running and locked to SYSCLK
5410B–HIREL–09/05
11
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