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8951 데이터시트 PDF




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부품번호 8951 기능
기능 8-Bit Microcontroller
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8951 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Features
Compatible with MCS-51Products
4 Kbytes of In-System Reprogrammable Flash Memory
Endurance: 1,000 Write/Erase Cycles
Fully Static Operation: 0 Hz to 24 MHz
Three-Level Program Memory Lock
128 x 8-Bit Internal RAM
32 Programmable I/O Lines
Two 16-Bit Timer/Counters
Six Interrupt Sources
Programmable Serial Channel
•• Low Power Idle and Power Down Modes
Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4
Kbytes of Flash Programmable and Erasable Read Only Memory (PEROM). The
device is manufactured using Atmel’s high density nonvolatile memory technology
and is compatible with the industry standard MCS-51instruction set and pinout.
The on-chip Flash allows the program memory to be reprogrammed in-system or by
a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU
with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer
which provides a highly flexible and cost effective solution to many embedded control
applications.
Pin Configurations
(continued)
PDIP/Cerdip
INDEX
CORNER
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
PQFP/TQFP
4 44 34 24 14 03 93 83 73 63 53 4
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
1
21
31
41
51
61
71
1
8
9
2
0
2
12
2
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
X TA L 2
X TA L 1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 P0.0 (AD0)
38 P0.1 (AD1)
37 P0.2 (AD2)
36 P0.3 (AD3)
35 P0.4 (AD4)
34 P0.5 (AD5)
33 P0.6 (AD6)
32 P0.7 (AD7)
31 EA/VPP
30 ALE/PROG
29 PSEN
28 P2.7 (A15)
27 P2.6 (A14)
26 P2.5 (A13)
25 P2.4 (A12)
24 P2.3 (A11)
23 P2.2 (A10)
22 P2.1 (A9)
21 P2.0 (A8)
PLCC/LCC
INDEX
CORNER
P1.5
P1.6
P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
6 4 2 44 42 40
7 5 3 1 43 4139
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
11781 92 02 12 22 32 42 52 62 72289
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
8-Bit
Microcontroller
with 4 Kbytes
Flash
AT89C51
0265E




8951 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
Pin Description (Continued)
When the AT89C51 is executing code from external pro-
gram memory, PSEN is activated twice each machine cy-
cle, except that two PSEN activations are skipped during
each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to VCC for internal program execu-
tions.
This pin also receives the 12-volt programming enable
voltage (VPP) during Flash programming, for parts that re-
quire 12-volt VPP.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use
as an on-chip oscillator, as shown in Figure 1. Either a
quartz crystal or ceramic resonator may be used. To drive
the device from an external clock source, XTAL2 should
be left unconnected while XTAL1 is driven as shown in
Figure 2. There are no requirements on the duty cycle of
the external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop, but
minimum and maximum voltage high and low time specifi-
cations must be observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hard-
ware reset, the device normally resumes program execu-
tion, from where it left off, up to two machine cycles before
the internal reset algorithm takes control. On-chip hard-
Figure 1. Oscillator Connections
C2
XTAL2
C1
XTAL1
GND
Notes: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Figure 2. External Clock Drive Configuration
Status of External Pins During Idle and Power Down
Mode
Idle
Idle
Power Down
Power Down
Program Memory
Internal
External
Internal
External
ALE
1
1
0
0
PSEN
1
1
0
0
PORT0
Data
Float
Data
Float
PORT1
Data
Data
Data
Data
PORT2
Data
Address
Data
Data
PORT3
Data
Data
Data
Data
4 AT89C51

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8951 전자부품, 판매, 대치품
AT89C51
www.DataSheet4U.com
Figure 3. Programming the Flash
A0 - A7
ADDR.
OOOOH/OFFFH
A8 - A11
AT89C51
P1 VCC
P2.0 - P2.3 P0
P2.6
SEE FLASH
PROGRAMMING
MODES TABLE
P2.7
P3.6
P3.7
ALE
XTAL 2
EA
+5V
PGM
DATA
PROG
VIH/VPP
Figure 4. Verifying the Flash
ADDR. A0 - A7
OOOOH/0FFFH
A8 - A11
AT89C51
P1 VCC
P2.0 - P2.3 P0
P2.6
SEE FLASH
PROGRAMMING
MODES TABLE
P2.7
P3.6
P3.7
ALE
XTAL 2
EA
+5V
PGM DATA
(USE 10K
PULLUPS)
VIH
4-24 MHz
4-24 MHz
XTAL 1
GND
RST
PSEN
VIH
XTAL 1
GND
RST
PSEN
VIH
Flash Programming and Verification Characteristics
TA = 21°C to 27°C, VCC = 5.0 ± 10%
Symbol
VPP(1)
IPP(1)
Parameter
Programming Enable Voltage
Programming Enable Current
1/tCLCL
Oscillator Frequency
tAVGL
Address Setup to PROG Low
tGHAX
Address Hold After PROG
tDVGL
Data Setup to PROG Low
tGHDX
Data Hold After PROG
tEHSH
P2.7 (ENABLE) High to VPP
tSHGL
tGHSL(1)
VPP Setup to PROG Low
VPP Hold After PROG
tGLGH
PROG Width
tAVQV
Address to Data Valid
tELQV
ENABLE Low to Data Valid
tEHQV
Data Float After ENABLE
tGHBL
PROG High to BUSY Low
tWC Byte Write Cycle Time
Note: 1. Only used in 12-volt programming mode.
Min
11.5
4
48tCLCL
48tCLCL
48tCLCL
48tCLCL
48tCLCL
10
10
1
0
Max
12.5
1.0
24
110
48tCLCL
48tCLCL
48tCLCL
1.0
2.0
Units
V
mA
MHz
µs
µs
µs
µs
ms
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