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PDF STP16CPP05 Data sheet ( Hoja de datos )
| Número de pieza | STP16CPP05 | |
| Descripción | Low voltage 16-bit constant current LED sink driver | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STP16CPP05
Low voltage 16-bit constant current LED sink driver
Features
■ 16 constant current output channels
■ Adjustable output current through external
resistor
■ Output current: 3-40 mA
■ Serial data in/parallel data ouT
■ 3.3 V or 5 V supply voltage
■ Max clock frequency 30 MHz
■ Schmitt-trigger input
■ ESD protection 2 kV HBM
■ Thermal shutdown
Description
The STP16CPP05 is a monolithic, low voltage,
low current power 16-bit shift register designed for
LED panel displays. The STP16CPP05 contains a
16-bit serial-in, parallel-out shift register that
feeds a 16-bit, D-type storage register. In the
output stage, sixteen regulated current sources
provide from 3 mA to 40 mA constant current to
drive the LEDs.
The output current setup time is 40 ns (typ), thus
improving the system performance.
The LEDs' brightness can be controlled by using
an external resistor to adjust the STP16CPP05
output current.
QSOP-24
SO-24
TSSOP24
TSSOP24
(exposed pad)
The STP16CPP05 guarantees a 20 V output
driving capability, allowing users to connect more
LEDs in series.The high clock frequency, 30 MHz,
makes the device suitable for high data rate
transmission. The 3.3 V voltage supply is useful in
applications that interface with a 3.3 V micro
controller.
Table 1. Device summary
Order codes
STP16CPP05MTR
STP16CPP05TTR
STP16CPP05XTTR
STP16CPP05PTR
February 2009
Package
SO-24
TSSOP24
TSSOP24 exposed pad
QSOP-24
Rev 1
Packaging
1000 parts per reel
2500 parts per reel
2500 parts per reel
2500 parts per reel
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Electrical ratings
2.3 Recommended operating conditions
Table 6. Recommended operating conditions at 25 °C
Symbol
Parameter
Test conditions
Min Typ Max Unit
VDD Supply voltage
3.0 5.5 V
VO Output voltage
20 V
IO Output current
OUTn
3 40 mA
IOH Output current
SERIAL-OUT
+1 mA
IOL Output current
SERIAL-OUT
-1 mA
VIH Input voltage
0.7 VDD
VDD+0.3 V
VIL Input voltage
-0.3 0.3 VDD V
twLAT LE pulse width
20 ns
twCLK CLK pulse width
16 ns
twEN OE pulse width
tSETUP(D) Setup time for DATA
VDD = 3.3 V to 5.0 V
70
5
ns
ns
tHOLD(D) Hold time for DATA
5 ns
tSETUP(L) Setup time for LATCH
fCLK Clock frequency
Cascade operation (1)
15
ns
30 MHz
1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please
considered the timings carefully.
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Figure 9. Clock, serial-in, serial-out
Timing diagrams
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| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet STP16CPP05.PDF ] | |
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