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FAN9612 데이터시트 PDF




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부품번호 FAN9612 기능
기능 Interleaved Dual BCM PFC Controller
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FAN9612 데이터시트, 핀배열, 회로
www.DataSheet4U.com
PRELIMINARY
February 2009
FAN9612
Interleaved Dual BCM PFC Controller
Features
ƒ Low Total Harmonic Distortion, High Power Factor
ƒ 180° Out of Phase Synchronization
ƒ Automatic Phase Disable at Light Load
ƒ 1.8A Sink, 0.8A Source, High Current Gate Drivers
ƒ Trans-conductance (gM) Error Amplifier
ƒ Voltage-Mode Control with (VIN)2 Feed Forward
ƒ Closed-Loop Soft-Start with User-Programmable
Soft-Start Time for Reduced Overshoot
ƒ Minimum Restart Timer Frequency to Avoid Audible
Noise
ƒ Maximum Switching Frequency Clamp
ƒ Brown-Out Protection with Soft-Recovery
ƒ Non-Latching OVP on FB pin and Latching Second
Level Protection on OVP Pin
ƒ Open Feedback Protection
ƒ Over-Current & Power-Limit Protection for Each
Phase
ƒ Low Start-Up Current of 80-µA Typical
ƒ Works with DC, 50Hz to 400Hz ac Inputs
Applications
ƒ 100-1000W Off-line Power Supplies
ƒ Large Screen LCD-TV, PDP-TV, RP-TV Power
ƒ High-End Desktop PC and Server Power Supplies
ƒ 80-PLUS Certified Equipment
Description
The FAN9612 Interleaved Dual Boundary-Conduction-
Mode (BCM) Power-Factor-Correction Controller
operates two parallel-connected boost power trains 180º
out of phase. Interleaving extends the maximum
practical power level of the control technique from about
300W to greater than 800W. Unlike the continuous
conduction mode (CCM) technique often used at higher
power levels, BCM offers inherent zero-current switching
of the boost diodes (no reverse-recovery losses), which
permits the use of less expensive diodes without
sacrificing efficiency. Furthermore, the input and output
filters can be made smaller due to ripple current
cancellation and effective doubling of the switching
frequency.
The converters operate with variable frequency which is
a function of the load and the instantaneous input /
output voltages. The switching frequency is limited
between 18kHz and 600kHz. The Pulse Width
Modulators implement voltage-mode control with input
voltage feed forward. When configured for PFC
applications, the slow voltage regulation loop results in
constant on-time operation within a line cycle. This PWM
method combined with the BCM operation of the boost
converters provides automatic power factor correction.
The FAN9612 offers bias UVLO, input brown-out, input
over-voltage, over-current, open feedback, over-
temperature, output over-voltage and redundant latching
over-voltage protections. Furthermore, the converters’
output power is limited independently of the input RMS
voltage. Synchronization between the power stages is
maintained under all operating conditions. The FAN9612
is available in Lead(Pb)-Free 16-lead SOIC package.
Simplified Application Diagram
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
www.fairchildsemi.com




FAN9612 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
Block Diagram
PRELIMINARY
ZCD1 1
CHANNEL 1
VALLEY DETECTOR
ZCD2 2
CHANNEL 2
VALLEY DETECTOR
SYNCHRONIZATION
RESTART TIMERS
FREQUENCY CLAMPS
AB
5VB 3
5V
MOT 4
IMOT
VDD
5V
BIAS
K1 VI2N IMOT
5V
A
0.195V
1.25V
5V
AGND 5
SS 6
3VREF
K1 VI2N IMOT
5V
5uA
B
0.195V
16 CS1
UVLO
15 CS2
0.2V
VDD
14 VDD
RQ
SQ
A
RQ
SQ
B
13 DRV1
12 DRV2
11 PGND
COMP 7
FB 8
gm PHASE
Management
INPUT VOLTAGE SENSE
(Input Voltage Squarer,
Input UVLO, Brown-out)
10 VIN
2uA
PROTECTION LOGIC
(Open FB, Input Protections, OVP,
Latched OVP, Thermal Shutdown)
9 OVP
Figure 3. FAN9612 Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
4
www.fairchildsemi.com

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FAN9612 전자부품, 판매, 대치품
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PRELIMINARY
Electrical Characteristics
Unless otherwise noted, VDD = 12V, TJ = -40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Supply
ISTART_UP
IDD
IDD_DYM
VON
VOFF
Start-up Supply Current
Operating Current
Dynamic Operating Current (4)
UVLO Start Threshold Voltage
UVLO Stop Threshold Voltage
UVLO Hysteresis
Bias Regulator (C5VB = 0.1 µF)
V5VB
5VB Output Voltage
IOUT_MAX Maximum Output Current
Error Amplifier
Voltage Reference
VSS
Line Regulation
Temperature Stability
IBIAS Input Bias Current
IOUT_SRC
IOUT_SINK
VOH
VOL
gM
Output Source Current
Output Sink Current
Output High Voltage
Output Low Voltage
Transconductance
PWM
PWM Ramp Offset
Minimum On-Time
Maximum On-Time
VMOT Maximum On-time Voltage
tON,MAX Maximum On-Time
Restart Timer (4) (each channel)
fSW,RT Minimum Switching Frequency
Conditions
Min. Typ. Max. Unit
VDD = VON – 0.2V
Output Not Switching
fSW = 50 kHz; CLOAD = 2 nF
VDD Increasing
VDD Decreasing
80 110 µA
2.5 4 mA
3 5 mA
12 12.5 13
V
7.0 7.5 8.0
V
5.0 V
TA = 25°C; ILOAD = 1 mA
5.0 V
Total Variation over line, load,
and temperature
4.8
5.2 V
5.0 mA
TA = 25°C
(±1.4%) 2.95 3.0 3.05
V
Total Variation over line, load,
and temperature (±2.6%)
2.925
3.075 V
VDD = 10 V to 18 V
0.1 10 mV
VFB = 1V to 3 V;
|VSS VFB| 0.1 V
VSS = 3 V; VFB = 3.1 V
VSS = 3V; VFB = 2.9 V
20 mV
–0.5 0.5 µA
–10 µA
10 µA
ISINK < 100µA
(Note 1)
4.5 4.7 V5VB V
0.0 0.1 0.2
V
80 100 120 µmho
TA = 25°C
VFB > VSS
120 195 270 mV
0.0 µs
R = 125k
R = 125k; VVIN = 2.5V;
VCOMP > 4.5 V; TA = 25°C
1.23 1.25 1.27
4.6
V
µs
VFB > VPWM_OFFSET
15.5 kHz
© 2008 Fairchild Semiconductor Corporation
FAN9612 • Rev. 0.9.1E
7
www.fairchildsemi.com

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관련 데이터시트

부품번호상세설명 및 기능제조사
FAN9612

Interleaved Dual BCM PFC Controller

Fairchild Semiconductor
Fairchild Semiconductor

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