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6549CBZ 데이터시트, 핀배열, 회로
www.DataSheet4U.com
®
Data Sheet
September 22, 2006
ISL6549
FN9168.2
Single 12V Input Supply Dual Regulator —
Synchronous Rectified Buck PWM and
Linear Power Controller
The ISL6549 provides the power control and protection for
two output voltages in high-performance applications. The
dual-output controller drives two N-Channel MOSFETs in a
synchronous rectified buck converter topology and one
N-Channel MOSFET in a linear configuration. The controller is
ideal for applications where regulation of both the processing
unit and memory supplies is required.
The synchronous rectified buck converter incorporates
simple, single feedback loop, voltage-mode control with fast
transient response. Both the switching regulator and linear
regulator provide a maximum static regulation tolerance of
±1% over line, load, and temperature ranges. Each output is
user-adjustable by means of external resistors.
An integrated soft-start feature brings both supplies into
regulation in a controlled manner. Each output is monitored
via the FB pins for undervoltage events. If either output drops
below 75% of the nominal output level, both converters are
shut off and go into retry mode.
The ISL6549 is available in a 14 Ld SOIC package,
16 Ld QSOP, or 16 Ld 4x4 QFN packages.
Related Literature
• Technical Brief TB363 Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)
Ordering Information
Features
• Single 12V bias supply (no 5V supply is required)
• Provides two regulated voltages
- One synchronous rectified buck PWM controller
- One linear controller
• Both controllers drive low cost N-Channel MOSFETs
• Small converter size
- Adjustable frequency 150kHz to 1MHz
- Small external component count
• Excellent output voltage regulation
- Both outputs: ±1% over temperature
• 12V down conversion
• PWM and linear output voltage range: down to 0.8V
• Simple single-loop voltage-mode PWM control design
• Fast PWM converter transient response
- High-bandwidth error amplifier
• Undervoltage fault monitoring on both outputs
• Pb-free plus anneal available (RoHS compliant)
Applications
Processor and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
PART NUMBER
PART MARKING
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
ISL6549CB
ISL6549CB
0 to 70
14 Ld SOIC
M14.15
ISL6549CBZ (Note)
6549CBZ
0 to 70
14 Ld SOIC (Pb-free)
M14.15
ISL6549CR
ISL6549CR
0 to 70
16 Ld 4x4 QFN
L16.4x4
ISL6549CRZ (Note)
6549CRZ
0 to 70
16 Ld 4x4 QFN (Pb-free)
L16.4x4
ISL6549CA
ISL6549CA
0 to 70
16 Ld QSOP
M16.15A
ISL6549CAZ (Note)
6549CAZ
0 to 70
16 Ld QSOP (Pb-free)
M16.15A
ISL6549CAZA (Note)
6549CAZ
0 to 70
16 Ld QSOP (Pb-free)
M16.15A
ISL6549IBZ (Note)
6549IBZ
-40 to 85
14 Ld SOIC (Pb-free)
M14.15
ISL6549IRZ (Note)
6549IRZ
-40 to 85
16 Ld 4x4 QFN (Pb-free)
L16.4x4
ISL6549IAZ (Note)
6549IAZ
-40 to 85
16 Ld QSOP (Pb-free)
M16.15A
ISL6549LOW-EVAL1
Evaluation Board 1-5A
ISL6549HI-EVAL1
Evaluation Board up to 20A
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.




6549CBZ pdf, 반도체, 판매, 대치품
ISL6549
www.ADabtasSohleuette4UM.caomximum Ratings
VCC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
PVCC5, VCC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
VCC5 (if used with external supply). . . . . . . . . . . GND - 0.3V to +6V
BOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +27V
PHASE. . . . . . . . . . . . . . . . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V
VBOOT - VPHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V
UGATE. . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to PVCC5 + 0.3V
LDO_DR . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC12 + 0.3V
FB, LDO_FB, COMP, FS_DIS . . . . . . . GND - 0.3V to VCC5 + 0.3V
ESD Classification
Human Body Model (Per JESD22-A114C) . . . . . . . . . . . . . . Class 2
Machine Model (Per EIA/JESD22-A115-A) . . . . . . . . . . . . . .Class B
Charge Device Model (Per JESD22-C101C). . . . . . . . . . . . Class IV
Thermal Information
Thermal Resistance
SOIC Package (Note 1) . . . . . . . . . . . .
QFN Package (Notes 2, 3). . . . . . . . . .
QSOP Package (Note 1) . . . . . . . . . . .
θJA (°C/W)
105
52
110
θJC (°C/W)
N/A
14
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
External Supply Voltage on VCC5 . . . . . . . . . . . . . . . . . . +5.0V ±5%
Supply Voltage on VCC12 . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range (C). . . . . . . . . . . . . . . . . . 0°C to 70°C
Ambient Temperature Range (I) . . . . . . . . . . . . . . . . -40°C to +85°
Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, unless otherwise noted. VCC12 = 12V
Temperature = 0 to +70°C (typical = +25°C) for Commercial; Temperature = -40 to + 85°C (typical = +25°C) for
Industrial. Refer to Block Diagram, Simplified Power System Diagram, and Typical Application Schematic.
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply Current VCC12 (disabled)
Nominal Supply Current VCC5 (disabled)
Nominal Supply Current VCC12
(includes PVCC5 current)
Nominal Supply Current VCC5
Maximum PVCC5 Current Available (Note 5)
VCC12 to PVCC5 Current Limit (Note 5)
PVCC5 Voltage
POWER-ON RESET
Rising VCC5 Threshold
Falling VCC5 Threshold
Rising VCC12 Threshold
Falling VCC12 Threshold
OSCILLATOR AND SOFT-START
Switching Frequency
SYMBOL
ICC12 dis
ICC5 dis
ICC12
ICC5
IPVCC5
IPVCC5CL
VPVCC5
FOSC
TEST CONDITIONS
UGATE, LGATE and LDO_DR open;
FS_DIS = GND
UGATE, LGATE and LDO_DR open;
FS_DIS = GND (Note 4)
UGATE, LGATE and LDO_DR open;
FOSC = 620kHz
UGATE, LGATE and LDO_DR open;
FOSC = 620kHz
ISL6549C; No external load
ISL6549I; No external load
VCC12 = 12V
VCC12 = 12V
VCC5 = 5V
VCC5 = 5V
ISL6549C; RFS_DIS = 45.3k
ISL6549I; RFS_DIS = 45.3k
MIN TYP MAX UNITS
2 3 mA
5 7.5 mA
12 18 mA
4 6 mA
100 mA
150 mA
4.95 5.25
5.8
V
4.85 5.25
5.8
3.7 4.2 4.5 V
3.3 3.8 4.1 V
8.8 9.5 10.0 V
7.0 7.5 8.0 V
540 620 700 kHz
525 620 700 kHz
4 FN9168.2
September 22, 2006

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6549CBZ 전자부품, 판매, 대치품
ISL6549
www.DDaetasSchereitp4Uti.coonm
Operation Overview
The ISL6549 monitors and precisely controls two output
voltage levels. Refer to the “Block Diagram” on page 2,
“Simplified Power System Diagram” on page 3, and “Typical
Application Schematic” on page 3. The controller is intended
for use in applications where only a 12V bias input is
available. The IC integrates both a standard buck PWM
controller and a linear controller. The PWM controller
regulates the output voltage (VOUT1) to a level programmed
by a resistor divider. The linear controller is designed to
regulate the lower current local memory voltage (VOUT2)
through an external N-Channel MOS pass transistor.
Internal PVCC5 Regulator
The preferred and recommended configuration is as follows:
+12V to VCC12 pin, a resistor (~10) between PVCC5 and
VCC5 pins, and decoupling caps on all three pins to ground.
This creates the PVCC5 voltage for the gate drivers, and
externally filters it for bias on the VCC5 pin. It also guarantees
that all 3 voltages track each other during power-up and
power-down.
The PVCC5 pin cannot be used as an input and it should not
be used as an output for other circuits; its current capability is
reserved for the gate drivers and VCC5 bias. Similarly, the
VCC5 pin should not be used as an output. Although not
preferred, the VCC5 pin can be used with an external 5V
supply (±5%). However, proper precautions must be followed,
which mainly have to do with proper sequencing, to prevent
latch-up or related problems. Note in the power-up diagram
(Figure 1), the 5V lags the 12V by a few msecs and a volt or
so; that is expected. Both the VCC12 and VCC5 pins must
exceed their rising POR trip points before the soft-start is
enabled; the trip order is not important as long as both have
some voltage. The 12V can be present with no 5V at all, but
the 5V should not precede the 12V. Similarly, on power down,
the 5V should discharge with or before the 12V.
Under normal operation, the internal regulator can supply up
to 100mA (which includes the VCC5 bias current, with the
resistor between the pins). The amount of current is
determined primarily by the switching parameters: the
oscillator frequency and the loading of the FET gates.
Overloading of the internal regulator is not recommended;
even if there is enough current, the gate driver waveforms
may be degraded. See “Switcher FET Considerations” on
page 13 for more details.
The PVCC5 pin has a current limit that provides some
protection against a shorted gate driver dragging down the
12V rail. The temperature of the IC will increase as the current
and corresponding on-chip power dissipation increases.
There is no thermal shutdown, so even if the current limit is
effective, the IC can be subject to very high temperatures. If
the current limit is exceeded, the regulator voltage will likely
collapse, shutting down everything until the load current is
reduced or removed.
Initialization
The ISL6549 automatically initializes upon application of input
power (at the VCC12) pin. The ISL6549 creates its own
PVCC5 and VCC5 supplies for internal use. The POR
function continually monitors the input bias supply voltage at
the VCC12 and VCC5 pins. The POR function initiates soft-
start operation after both these supply voltages exceed their
POR rising threshold voltages.
Soft-Start
The POR function initiates the digital soft-start sequence. Both
the linear regulator error amplifier and PWM error amplifier
reference inputs are forced to track a voltage level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator regulates the output relative
to the tracked soft-start voltage, slowly charging the output
capacitor(s). Simultaneously, the linear output follows the
smooth ramp of the soft-start function into normal regulation.
Figure 1 shows the soft-start sequence. Both the VCC12 and
VCC5 pins must be above their respective rising POR trip
points. In most cases, as shown here, the last one exceeding
its threshold is the VCC12 around 9.5V. The ramp time is
based on the internal oscillator period multiplied by 4096. So
for a 600kHz (1.67µs) example, the soft-start ramp time would
be 6.8ms.
VCC12 > 9.5V
VCC12 (2V/DIV)
GND>
VCC5 (2V/DIV)
VOUT1 (1V/DIV)
VOUT2 (1V/DIV)
FIGURE 1. 12V POWER-UP INTO SOFT-START
Figure 2 shows more detail of the output ramps, by increasing
the time and voltage resolution. The clock for the DAC
producing the steps is approximately 9.4kHz (600kHz/64), so
each step is just over 100µs long. The step voltage is 1/64 of
the final value for each output; around 31mV for VOUT1 and
15.6mV for VOUT2 in this example. By providing many small
steps of voltage (and current) that effectively charge the
output capacitor, the potentially large peak current resulting
from a sudden, uncontrolled voltage rise are eliminated, by
spreading it out over the whole ramp time.
7 FN9168.2
September 22, 2006

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6549CBZ

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