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PDF SYS321000LK-025 Data sheet ( Hoja de datos )

Número de pieza SYS321000LK-025
Descripción 1M x 32 SRAM MODULE
Fabricantes MOSAIC 
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1M x 32 SRAM MODULE
SYS321000ZK/LK - 012/015/020/025
Issue 1.5 : December 1998
Description
The SYS321000ZK/LK is a industry standard
plastic 32Mbit Static RAM Module housed in a 72
pin plastic SIMM & ZIP package organised as 1M
x 32. The module utilises fast SRAMs housed in
SOJ packages, and uses double sided surface
mount techniques to achieve a very high density
module.
The module has four Chip Selects, which allow
reading and writing to individual bytes or words.
The pins PD0-3, are used to identify module
memory density in applications where alternative
modules can be interchanged.
Features
• Access Times of 12/15/20/25 ns.
• 72 Pin ZIP, SIMM package
• 5 Volt Supply ± 10%.
• Low Power Dissipation:
Average (min cycle)
7.48 W (Max).
Standby -L Version (CMOS) 22 mW (Max).
• Completely Static Operation.
• On-board Supply Decoupling Capacitors.
• Equivalent to EDI part EDI8F321024C, IDT part
IDT7MP4120, and Cypress part CYM1851.
Block Diagram
A0 - A19
WE
OE
CS1
1Mx 4
SRAM
D0 - D3
1Mx 4 D8 - D11
SRAM
CS2
1Mx 4 D16 - D19
SRAM
CS3
1Mx 4 D24 - D27
SRAM
CS4
1Mx 4 D4 - D7
SRAM
1Mx 4
SRAM
D12 - D15
1Mx 4 D20 - D23
SRAM
1Mx 4
SRAM
D28 - D31
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Presence Detect
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
A0 - A19
D0 - D31
CS1-4
PD0-3
WE
OE
NC
VCC
GND
Pin Definition
ZIP TOP VIEW
NC
PD3
PD0
D0
D1
D2
D3
VCC
A7
A8
A9
D4
D5
D6
D7
WE
A14
CS1
CS3
A16
GND
D16
D17
D18
D19
A10
A11
A12
A13
D20
D21
D22
D23
GND
A19
NC
2
1
3
45
6
8
10
12
14
16
18
7
9
11
13
15
17
19
20
22
24
26
28
30
32
21
23
25
27
29
31
33
34
36
35
38
40
42
44
37
39
41
43
45
46 47
48
50
52
54
56
58
49
51
53
55
57
59
60 61
62
63
64
68
70
72
63
65
67
69
71
PD0=PD2=GND
PD1=PD3=OPEN
SIMM
NC
PD2
GND
PD1
D8
D9
D10
D11
A0
A1
A2
D12
D13
D14
D15
GND
A15
CS2
CS4
A17
OE
D24
D25
D26
D27
A3
A4
A5
VCC
A6
D28
D29
D30
D31
A18
NC
NC
NC
PD2
PD3
GND
PD0
PD1
D0
D8
D1
D9
D2
D10
D3
D11
VCC
A0
A7
A1
A8
A2
A9
D12
D4
D13
D5
D14
D6
D15
D7
GND
WE
A15
A14
CS2
CS1
CS4
CS3
A17
A16
OE
GND
D24
D16
D25
D17
D26
D18
D27
D19
A3
A10
A4
A11
A5
A12
VCC
A13
A6
D20
D28
D21
D29
D22
D30
D23
D31
GND
A18
A19
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Package Details
Plastic 72 Pin SIMM
Plastic 72 Pin ZIP

1 page




SYS321000LK-025 pdf
SYS321000ZK/LK - 012/015/20/25
Read Cycle Timing Waveform (1,2)
www.DataSheet4U.com
Address
OE
CS1~4
Dout
t RC
t AA
t OE
t OLZ
t ACS
t CLZ (4,5)
ISSUE 1.5 : December 1998
t OH
tOHZ (3)
Data Valid
tCHZ (3,4,5)
Don't
care.
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform(1,4)
Address
OE
CS1~4
WE
Dout
Din
tWC
t AS(6)
t AW
t CW
t WR(7)
t OHZ(3,9)
High-Z
t WP(2)
High-Z
tOW
t DW
t DH
Data Valid
Don't
Care
(8)
5

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