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SYS32512ZK-010 데이터시트 PDF




MOSAIC에서 제조한 전자 부품 SYS32512ZK-010은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 SYS32512ZK-010 기능
기능 512 K x 32 Static RAM
제조업체 MOSAIC
로고 MOSAIC 로고


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SYS32512ZK-010 데이터시트, 핀배열, 회로
www.DataSheet4U.com
SYS32512ZK/LK - 010/012/015
Issue 5.0 June 1999
Description
The SYS32512 is a 512K x 8 SRAM module in a ZIP
(ZK) or SIMM (LK & LKXA) packages with access
times of 12 and 15ns, with 10ns parts under
development. The device is available to
commercial and industrial temperature grade.
The LK SIMM package is designed for standard
SIMM sockets. The LKXA is designed to fit both
angled and standard sockets.
Block Diagram
A0~A18
/WE
/OE
/CS1
Features
• Access times of 10, 12 and 15ns.
• 5V + 10%.
• Commercial and Industrial temperature grades
• 72 pin ZIP and SIMM packages.
• Industry standard footprint.
• Power dissipation.
• Operating Power (32 Bit) 4.62W (max)
• Low power standby. (TTL) 1.32W (max)
(CMOS) 330mW (max)
• Completely Static Operation.
/CS2
/CS3
/CS4
Pin Definition
See page 2.
Pin Functions
512K x 8
SRAM
D0~7
512K x 8
SRAM
D8~15
512K x 8
SRAM
D16~23
512K x 8
SRAM
D24~D31
Package Details
Plastic 72 Pin ZIP (ZK)
Max. Dimensions (mm) - 97.80 x 20.61 x 5.90
Plastic 72 Pin SIMM (LK)
Max. Dimensions (mm) - 108.08 x 15.00 x 5.25
Plastic 72 Pin SIMM (LKXA)
Max. Dimensions (mm) - 108.08 x 20.32 x 4.55
Description
Address Input
Data Input/Output
Chip Select
Presence Detect
Write Enable
Output Enable
No Connect
Power
Ground
Signal
A0~A18
D0~D31
/CS1~4
PD0~3
/WE
/OE
NC
VCC
VSS




SYS32512ZK-010 pdf, 반도체, 판매, 대치품
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Capacitance
(VCC = 5.0V, TA = 25OC)
Param eter
Symbol Test Condition Min Typ Max Unit
Input Capacitance, (Address, /OE, /WE)
C IN1
V IN=0V
- - 32 pF
Input Capacitance, (Other)
C IN2
V IN=0V
- - 7 pF
O utput C apacitance, 8 bit m ode (worst case)
C I/O
V I/O=0V
- - 40 pF
Note : These Parameters are calculated not measured.
Test Conditions
Output Load
Input pulse levels : 0V to 3.0V
Input rise and fall times : 3ns
Input and Output timing reference levels : 1.5V
Output Load : See Load Diagram.
VCC = 5V+10%
I/O Pin
166Ω
1.76V
30pF
Operation Truth Table
/CS /OE /WE
HXX
L LH
LHL
LLL
L HH
Data Pins
High Impedence
Data Out
Data In
Data In
High Impedence
Supply Current
ISB1,ISB2
ICC1
ICC1
ICC1
ISB1,ISB2
Mode
Standby
Read
Write
Write
High Z
Notes : H=VIH : L=VIL : X=VIH or VIL
PAGE 4
Issue 5.0 June 1999

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SYS32512ZK-010 전자부품, 판매, 대치품
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Write Cycle 1
(/OE = Clock)
Address
/OE
/CS
/WE
Data In
Data Out
tWC
tAW
tCW(3)
tWR(5)
tAS(4)
High Z
tOHZ(6)
tWP(2)
tDW
Valid Data
High Z(8)
tDH
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ;
A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of /CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
11 ./CS=/CS1~4
PAGE 7
Issue 5.0 June 1999

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