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기능 Arinc 429 Transceiver
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DEI1016B 데이터시트, 핀배열, 회로
Device
www.DaEtaSnheegt4Ui.ncomeering
Incorporated
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
DEI1016/DEI1016A/DEI1016B
/DEI1016C ARINC 429
Transceiver Family
Features
Two Receivers and One Transmitter
Industry Standard Pin for Pin Replacement Part
Wraparound Self-Test mode
Word length can be configured for 25 bit or 32 bits operation
Parity Status and generation of Receive and Transmit Words
8 Word Transmitter buffer
Low Power CMOS processing
Supports multiple ARINC protocols: 429, 571, 575, 706
Available in extended (-55/+85°C) and Military (-55/+125°C) temperature ranges
General Description:
The DEI1016 provides an interface between a standard avionics type serial digital data bus and a 16-bit-wide digital data bus. The
interface circuit consists of a single channel transmitter with an 8X32 bit buffer, two independent receive channels, and a host
programmable control register to select operating options. The two receiver channels operate identically, each providing a direct
electrical interface to an ARINC data bus.
The transmitter circuit contains an 8 word by 32 bit buffer memory and control logic which allows the host to write a block of data
into the transmitter. The block of data is transmitted automatically by enabling the transmitter with no further attention by the host
computer. Data is transmitted in TTL format on the D0(A)/D0(B) output pins. The signal format is compatible with DEI’s extensive
line of ARINC 429 Line drivers for easy connection to the ARINC data bus.
ARINC 429
Receive 0
ARINC 429
Receive 1
ARINC 429
Transmit
© 2005 Device Engineering Inc.
Receive
Decoder
Receive
Decoder
Transmit
Encoder
32
Control
Register
32
32
16
Host
Interface
32
TX FIFO
8 Words X 32 Bits
/DR1, /DR2
TXR
/OE1, /OE2
/LD1, /LD2
ENTX
/LDCW
/DBCEN
/MR
16 DATA BUS
Figure 1: DEI1016 Block Diagram
Page 1 of 17
DS-MW-01016-01 Rev A
01/07/2005




DEI1016B pdf, 반도체, 판매, 대치품
wwwF.DuantacSthieoent4aUl.cDomescription:
The DEI 1016 supports a number of various options
which are selected by data written into the control
register. Data is written into the control register from the
16-bit data bus when the /LDCW signal is pulsed to a
logic “0”. The twelve control bits control the following
functions:
1) Word Length (32 or 25 bits)
2) Transmitter bit 32 (Parity or Data)
3) Wrap around self test.
4) Source Destination code checking of received data.
5) Transmitter parity (even or odd)
6) Transmitter and Receiver data rate (100 or 12.5 kbps)
Table 5: Control Register Format
BIT SYMBOL BIT SYMBOL
D15 (MSB) WLSEL
D7 X1
D14 RCVSEL
D6 SDENB1
D13 TXSEL
D5 /SLFTST
D12 PARCK
D4 PAREN
D11 Y2
D3 NOT USED
D10 X2
D2 NOT USED
D9 SDENB2 D1 NOT USED
D8 Y1 D0 NOT USED
Table 6: DEI1016 Control Word
NAME
PAREN
DATA BIT
DESCRIPTION
Transmitter Parity Enable. Enables parity bit insertion into transmitter data bit 32. Parity is always
D4 inserted if /DBCEN is open or HI. If /DBCEN is LO, Logic “0” on PAREN inserts data on bit 32, and
Logic “1” on PAREN inserts parity on bit 32.
/SLFTST1
Self Test Enable. Logic “0” enables a “wrap around” test mode which internally connects the transmitter
D5
outputs to both receiver inputs, bypassing the receiver front end. The test data is inverted before going
into receiver 2 so that its data is the complement of that received by receiver 1. The transmitter output is
active during test mode.
SDEN12
X1, Y12
D6
D7, D8
S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for receiver 1.
S/D compare code RX1. If the receiver 1 S/D code check is enabled (SDENB1=1), then incoming
receiver data S/D fields will be compared to X1, Y1. If they match, the word will be accepted by receiver
1; if not, it will be ignored. X1 (D7) is compared to serial data bit 9, Y1 (D8) is compared to serial data
bit 10.
SDEN22
X2, Y22
D9 S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for receiver 1.
S/D compare code RX2. If the receiver 2 S/D code check is enabled (SDENB2=1), then incoming
D10, D11
receiver data S/D fields will be compared to X2, Y2. If they match, the word will be accepted by receiver
2; if not, it will be ignored. X2 (D10) is compared to serial data bit 9, Y2 (D11) is compared to serial
data bit 10.
PARCK
D12
Parity Check Enable. Logic “1” inverts the transmitter parity bit for test of parity circuits. Logic “0”
selects normal odd parity; logic “1” selects even parity.
TXSEL3
Transmitter Data Rate Select. Logic “0” sets the transmitter to the HI data rate. HI rate is equal to the
D13 clock rate divided 10. Logic “1” sets the transmitter to the LO data rate. LO rate is equal to the clock rate
divided by 80.
RCVSEL4
Receiver Data Rate Select. Logic “0” sets both receivers to accept the HI data rate. The nominal HI data
D14 rate is the input clock divided by 10. Logic “1” sets both receivers to the LO data rate. The nominal LO
data rate is the input clock divided by 80.
WLSEL5
D15
Word Length Select. Logic “0” sets the transmitter and receivers to a 32 bit word format. Logic ”1” sets
them to a 25 bit word format.
NOT USED
D0-D3
When writing to the control register, the four “not used bits” are “don’t care” bits. These four bits will not
be used on the chip.
NOTES
1) The test mode should always conclude with ten null’s. This step prevents both receivers from accepting invalid data.
2) SDENBn, Xn & Yn should be changed within 20 bit times after /DRn goes low and the bit stream has been read, or within 30 bit times after a
master reset has been removed.
3) TXSEL should only be changed during the time that TXR is high or Master Reset is low.
4) RCVSEL should be changed only during a Master Reset pulse. If changed at any other time, then the next bit stream from both Receiver 1 and
Receiver 2 should be ignored.
5) When the control word is written the effect of the WLSEL bit will take effect immediately on the first complete ARINC word received or
transmitted following the control word write operation.
© 2005 Device Engineering Inc.
Page 4 of 17
DS-MW-01016-01 Rev A
01/07/2005

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DEI1016B 전자부품, 판매, 대치품
FIFO Buffer (continued)
wwwT.DhaetabSuhfefeert4dUa.tcaomis transmitted until the last word in the buffer is
shifted out. At this time a transmitter ready signal (TXR) is set to a
logic “1” indicating that the buffer is empty and ready to receive up
to eight more data words. Writing into the buffer memory is
disabled when ENTX is set to logic “1”.
Transmitter Ready Signal (TXR)
The transmitter ready flag (TXR) is set to logic “0” with the first
occurrence of an /LD2 pulse to indicate that the buffer is not
empty.
Output Register
The output register is designed such that it can shift out a word of
25 bits or 32 bits. The length is controlled by control register bit
"WLSEL".
TX Word Gap Timer
The TX word gap timer circuit inserts a 4 bit time gap between
words. This gives a minimum requirement of a 29 bit time or a 36
bit time for each word transmission. The 4 bit time gap is also
automatically maintained when the next new block of data is
loaded into the buffer, which may take less than one bit time.
Parity Generator
The parity generator calculates either odd or even parity as
specified by control register bit "PARCK". Odd parity is normally
used; even parity is available to test the receiver parity check
circuit. Odd parity means that there is an odd number of 1's in the
25 or 32 bit serial word. Bit 8 of word one is replaced with a parity
bit if parity is selected by the control register bit "PAREN" and the
/DBCEN pin. Otherwise, bit 8 is passed through as data.
Transmitter Output
The transmitter driver outputs three TTL compatible signals: 1)
DO(A), 2) DO(B), and 3) TXCLK. DO(A) and DO(B) are the
transmitter data in two rail, return-to-zero format. DO(A) indicates
a logic "1" data bit by going to a "1" for the 1st half of a bit time,
then returning to "0" for the 2nd half; DO(B) remains at "0" for the
whole bit time. In the same fashion, DO(B) indicates a logic "0"
data bit by pulsing HI while DO(A) remains LO. A null bit is
indicated when both signals remain LO. It is illegal for both signals
to be logic "1". The TXCLK is a free running clock signal of 50%
duty cycle and in phase with transmitter data. The clock will
always be logic "1" during the first half of a bit time.
Power-Up Reset
An internal power-up reset circuit prevents erroneous data
transmission before an external master reset has been applied.
25-bit Word Operation:
The TRANSCEIVER implements a 25 bit word format which may
be used in non-ARINC applications to enhance data transfer rate.
The format is a simplified version of the 32 bit ARINC word and is
described in Figure 3. It consists of an 8 bit label, a 16 bit data
word, and a parity bit. The parity bit can optionally be replaced
with a 17th data bit. The Source/Destination code checking option
can be enabled in either receiver. It will operate on bits 9 and 10 of
the 25 bit word.
Self-Test Operation:
By selecting the control register bit (/SLFTST) self test option,
the user may perform a functional test of the TRANSCEIVER
and support circuitry. The user can write data into the
transmitter and it will be internally wrapped around into both
receivers. The user can then verify reception and integrity of
the data. The receiver line interface and the user's line drivers
will not be tested.
By setting the transmitter to use even parity, the user can test
the receiver's parity circuit operation.
Power-up reset and Master Reset:
The user must apply an active Lo pulse to the Master Reset pin
(/MR) after power up or upon system reset. Preceding the
master reset at power-up an internal power-up reset occurs
which will clear the transmitter such that no erroneous serial
data stream will be transmitted before master reset. Receivers,
control register, and internal control logic are reset by master
reset.
After resetting the device, the user must program the control
register before beginning normal operation. The control
register may be reprogrammed without additional reset pulses.
Processor Interface:
Figure 7 shows a typical reset and initialization sequence. The
user must pulse the /MR pin low to reset the device. To load
the Control Register from the data bus, the /LDCW pin is
pulsed low while the desired control data is applied on the data
bus.
Figure 5 shows a typical transmitter loading sequence. It
begins with the transmitter completing transmission of the
previous data block. The TXR flag goes HI to notify the user
that data may be loaded into the buffer. The user sets ENTX to
LO to disable the Transmitter and proceeds to load a total of
six ARINC words into the buffer. (Note that up to eight words
could have been loaded). The user then enables the transmitter
by setting ENTX to a logic "1" and the transmitter begins it's
sequence of sending out data words. Although not shown in the
figure, the transmitter loading sequence can be interrupted by
receiver reading cycle with no interference between the two
operations.
Figure 6 shows a typical receiver reading sequence. Both
receivers notify the user of valid data ready by setting their
respective /DRn lines to logic "0". The user responds by first
reading the two data words from Receiver 1 and then from
Receiver 2. The SEL line is normally a system address line and
may assume any state, but must be valid when the /OEn line is
pulsed low.
© 2005 Device Engineering Inc.
Page 7 of 17
DS-MW-01016-01 Rev A
01/07/2005

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