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PDF BUK9523-75A Data sheet ( Hoja de datos )
| Número de pieza | BUK9523-75A | |
| Descripción | logic level FET | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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BUK9523-75A; BUK9623-75A
TrenchMOS™ logic level FET
Rev. 01 — 10 October 2000
Product specification
1. Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™ technology, featuring very low on-state resistance.
Product availability:
BUK9523-75A in SOT78 (TO-220AB)
BUK9623-75A in SOT404 (D 2-PAK).
2. Features
s TrenchMOS™ technology
s Q101 compliant
s 175 °C rated
s Logic level compatible.
3. Applications
s Automotive and general purpose power switching:
c
c x 12 V, 24 V and 42 V loads
x Motors, lamps and solenoids.
4. Pinning information
Table 1: Pinning - SOT78, SOT404, simplified outline and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d)
mb mb
3 source (s)
mb mounting base;
connected to drain (d)
MBK106
123
SOT78 (TO-220AB)
2
1 3 MBK116
SOT404 (D2-PAK)
Symbol
d
g
MBB076
s
1 page  
Philips Semiconductors
www.DataSheet4U.com
BUK9523-75A; BUK9623-75A
TrenchMOS™ logic level FET
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified
Symbol Parameter
Conditions
Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown
ID = 0.25 mA; VGS = 0 V
voltage
Tj = 25 °C
75 − − V
Tj = −55 °C
70 − − V
VGS(th)
gate-source threshold voltage ID = 1 mA; VDS = VGS;
Figure 9
IDSS
IGSS
RDSon
drain-source leakage current
gate-source leakage current
drain-source on-state
resistance
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
VDS = 75 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±10 V; VDS = 0 V
VGS = 5 V; ID = 25 A;
Figure 7 and 8
1 1.5 2 V
0.5 − − V
− − 2.3 V
−
0.05 10
µA
− − 500 µA
− 2 100 nA
Dynamic characteristics
Tj = 25 °C
Tj = 175 °C
VGS = 4.5 V; ID = 25 A;
Tj = 25 °C
VGS = 10 V; ID = 25 A;
Tj = 25 °C
− 18 23 mΩ
− − 49 mΩ
− − 26 mΩ
− 17 22 mΩ
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
Ld
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
internal drain inductance
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 12
VDD = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 10 Ω;
from drain lead 6mm from
package to centre of die
−
−
−
−
−
−
−
−
2340
319
215
24
141
142
108
4.5
3120
383
295
−
−
−
−
−
pF
pF
pF
ns
ns
ns
ns
nH
from contact screw on
mounting base to centre of
die SOT78
−
3.5 −
nH
from upper edge of drain
mounting base to centre of
die SOT404
−
2.5 −
nH
Ls
internal source inductance from source lead to source
−
bond pad
7.5 −
nH
9397 750 07582
Product specification
Rev. 01 — 10 October 2000
© Philips Electronics N.V. 2000. All rights reserved.
5 of 15
5 Page 
Philips Semiconductors
www.DataSheet4U.com
10. Soldering
BUK9523-75A; BUK9623-75A
TrenchMOS™ logic level FET
handbook, full pagewidth
1.50
2.25 2.15
10.85
10.60
10.50
7.50
7.40
1.70
8.15 8.35
1.50
4.60
8.275
4.85
7.95
0.30
3.00
solder lands
solder resist
occupied area
solder paste
Dimensions in mm.
Fig 18. Reflow soldering footprint for SOT404.
5.40
8.075
0.20
5.08
1.20
1.30
1.55
MSD057
9397 750 07582
Product specification
Rev. 01 — 10 October 2000
© Philips Electronics N.V. 2000. All rights reserved.
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