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W9725G6IB 데이터시트 PDF




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부품번호 W9725G6IB 기능
기능 4M X 4 BANKS X 16 BIT DDR2 SDRAM
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W9725G6IB 데이터시트, 핀배열, 회로
W9725G6IB
4M × 4 BANKS × 16 BIT DDR2 SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................4
2. FEATURES ...........................................................................................................................................4
3. KEY PARAMETERS .............................................................................................................................5
4. BALL CONFIGURATION ......................................................................................................................6
5. BALL DESCRIPTION............................................................................................................................7
6. BLOCK DIAGRAM ................................................................................................................................8
7. FUNCTIONAL DESCRIPTION..............................................................................................................9
7.1 Power-up and Initialization Sequence ...................................................................................................9
7.2 Mode Register and Extended Mode Registers Operation ...................................................................10
7.2.1
Mode Register Set Command (MRS)...............................................................................10
7.2.2
Extend Mode Register Set Commands (EMRS) ..............................................................11
7.2.2.1
Extend Mode Register Set Command (1), EMR (1)................................................11
7.2.2.2
DLL Enable/Disable................................................................................................12
7.2.2.3
Extend Mode Register Set Command (2), EMR (2)................................................13
7.2.2.4
Extend Mode Register Set Command (3), EMR (3)................................................14
7.2.3
Off-Chip Driver (OCD) Impedance Adjustment ................................................................15
7.2.3.1
Extended Mode Register for OCD Impedance Adjustment ....................................16
7.2.3.2
OCD Impedance Adjust ..........................................................................................16
7.2.3.3
Drive Mode .............................................................................................................17
7.2.4
On-Die Termination (ODT)...............................................................................................18
7.2.5
ODT related timings .........................................................................................................18
7.2.5.1
MRS command to ODT update delay.....................................................................18
7.3 Command Function.............................................................................................................................20
7.3.1
Bank Activate Command..................................................................................................20
7.3.2
Read Command ...............................................................................................................20
7.3.3
Write Command ...............................................................................................................21
7.3.4
Burst Read with Auto-precharge Command.....................................................................21
7.3.5
Burst Write with Auto-precharge Command .....................................................................21
7.3.6
Precharge All Command ..................................................................................................21
7.3.7
Self Refresh Entry Command ..........................................................................................21
7.3.8
Self Refresh Exit Command .............................................................................................22
7.3.9
Refresh Command ...........................................................................................................22
7.3.10
No-Operation Command ..................................................................................................23
7.3.11
Device Deselect Command..............................................................................................23
7.4 Read and Write access modes ...........................................................................................................23
7.4.1
Posted CAS ....................................................................................................................23
7.4.1.1
Examples of posted CAS operation......................................................................23
Publication Release Date: Oct. 23, 2009
- 1 - Revision A04




W9725G6IB pdf, 반도체, 판매, 대치품
W9725G6IB
1. GENERAL DESCRIPTION
The W9725G6IB is a 256M bits DDR2 SDRAM, organized as 4,194,304 words × 4 banks × 16 bits.
This device achieves high speed transfer rates up to 800Mb/sec/pin (DDR2-800) for general
applications. W9725G6IB is sorted into two speed grades: -25 and -3. The -25 is compliant to the
DDR2-800 (6-6-6) specification, the -3 is compliant to the DDR2-667 (5-5-5) specification.
All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All
I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source
synchronous fashion.
2. FEATURES
z Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
z Double Data Rate architecture: two data transfers per clock cycle
z CAS Latency: 3, 4, 5 and 6
z Burst Length: 4 and 8
z Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
z Edge-aligned with Read data and center-aligned with Write data
z DLL aligns DQ and DQS transitions with clock
z Differential clock inputs (CLK and CLK )
z Data masks (DM) for write data
z Commands entered on each positive CLK edge, data and data mask are referenced to both edges
of DQS
z Posted CAS programmable additive latency supported to make command and data bus efficiency
z Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
z Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal
quality
z Auto-precharge operation for read and write bursts
z Auto Refresh and Self Refresh modes
z Precharged Power Down and Active Power Down
z Write Data Mask
z Write Latency = Read Latency - 1 (WL = RL - 1)
z Interface: SSTL_18
z Packaged in WBGA 84 Ball (8X12.5 mm2), using Lead free materials with RoHS compliant
Publication Release Date: Oct. 23, 2009
- 4 - Revision A04

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W9725G6IB 전자부품, 판매, 대치품
W9725G6IB
5. BALL DESCRIPTION
BALL NUMBER SYMBOL
M8,M3,M7,N2,N8,N3
,N7,P2,P8,P3,M2,P7
,R2
A0A12
L2,L3
BA0BA1
G8,G2,H7,H3,H1,H9
,F1,F9,C8,C2,D7,D3, DQ0DQ15
D1,D9,B1,B9
K9 ODT
F7,E8
LDQS,
LDQS
B7,A8
UDQS,
UDQS
L8 CS
FUNCTION
Address
Bank Select
DESCRIPTION
Provide the row address for active commands, and the column
address and Auto-precharge bit for Read/Write commands to select
one location out of the memory array in the respective bank.
Row address: A0A12.
Column address: A0A8. (A10 is used for Auto-precharge)
BA0BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Data Input
/ Output
Bi-directional data bus.
On Die Termination
Control
LOW Data Strobe
UP Data Strobe
ODT (registered HIGH) enables termination resistance internal to the
DDR2 SDRAM.
Data Strobe for Lower Byte: Output with read data, input with write
data for source synchronous operation. Edge-aligned with read data,
center-aligned with write data. LDQS corresponds to the data on
DQ0DQ7. LDQS is only used when differential data strobe mode
is enabled via the control bit at EMR (1)[A10 EMRS command].
Data Strobe for Upper Byte: Output with read data, input with write
data for source synchronous operation. Edge-aligned with read data,
center-aligned with write data. UDQS corresponds to the data on
DQ8DQ15. UDQS is only used when differential data strobe mode
is enabled via the control bit at EMR (1)[A10 EMRS command].
Chip Select
All commands are masked when CS is registered
HIGH. CS provides for external bank selection on systems with
multiple ranks. CS is considered part of the command code.
K7,L7,K3
B3,F3
RAS , CAS ,
WE
UDM
LDM
J8,K8
CLK,
CLK
K2
J2
A1,E1,J9,M9,R1
A3,E3,J3,N1,P9
A9,C1,C3,C7,C9,E9,
G1,G3,G7,G9
A7,B2,B8,D2,D8,E7,
F2,F8,H2,H8
A2,E2,L1,R3,R7,R8
J7
J1
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
VSSDL
VDDL
Command Inputs
Input Data Mask
Differential Clock
Inputs
Clock Enable
Reference Voltage
Power Supply
Ground
DQ Power Supply
DQ Ground
No Connection
DLL Ground
DLL Power Supply
RAS , CAS and WE (along with CS ) define the command being
entered.
DM is an input mask signal for write data. Input data is masked when
DM is sampled high coincident with that input data during a Write
access. DM is sampled on both edges of DQS. Although DM pins are
input only, the DM loading matches the DQ and DQS loading.
CLK and CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK
and negative edge of CLK . Output (read) data is referenced to the
crossings of CLK and CLK (both directions of crossing).
CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM.
VREF is reference voltage for inputs.
Power Supply: 1.8V ± 0.1V.
Ground.
DQ Power Supply: 1.8V ± 0.1V.
DQ Ground. Isolated on the device for improved noise immunity.
No connection.
DLL Ground.
DLL Power Supply: 1.8V ± 0.1V.
Publication Release Date: Oct. 23, 2009
- 7 - Revision A04

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W9725G6IB

4M X 4 BANKS X 16 BIT DDR2 SDRAM

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