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KK4052B 데이터시트 PDF




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부품번호 KK4052B 기능
기능 Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS
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KK4052B 데이터시트, 핀배열, 회로
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TECHNICAL DATA
KK4052B
Analog Multiplexer Demultiplexer
High-Performance Silicon-Gate CMOS
The KK4052B analog multiplexer/demultiplexer is digitally controlled
analog switches having low ON impedance and very low OFF leakage
current. Control of analog signals up to 20V peak-to-peak can be
achieved by digital signal amplitudes of 4.5 to 20V (if VCC - GND = 3V,
a VCC - VEE of up to 13 V can be controlled; for VCC - VEE level
differences above 13V a VCC - GND of at least 4.5V is required).
These multiplexer circuits dissipate extremely low quiescent power
over the full VCC -GND and VCC - VEE supply-voltage ranges,
independent of the logic state of the control signals. When a logic “1”is
present at the ENABLE input terminal all channels are off.
The IW4052 is a differential 4-channel multiplexer having two binary
control inputs. A and B, and an enable input. The two binary input signals
select 1 of 4 pairs of channels to turned on and connect the analog inputs
to the outputs.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
N SUFFIX
PLASTIC
16
1 D SUFFIX
16 SOIC
1
ORDERING INFORMATION
KK4052BN
Plastic DIP
KK4052BD
SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
Double-Pole, 4-Position
Plus Common Off
PIN 16 =VCC
PIN 7 = VEE
PIN 8 = GND
FUNCTION TABLE
Control Inputs
Enable
Select
BA
L LL
L LH
L HL
L HH
HX
H = high level
L = low level
X = don’t care
X
ON
Channels
Y0 X0
Y1 X1
Y2 X2
Y3 X3
None
1




KK4052B pdf, 반도체, 판매, 대치품
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KK4052B
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=20.0 ns)
Symbol
Parameter
VCC
V
tPHL(tPLH)
tPHL1(tPLH1)
tPZL1(tPZH1)
tPZL2(tPZH2)
tPLZ1(tPHZ1)
tPLZ2(tPHZ2)
CIN
CI/O
Maximum Propagation Delay , Analog Input to
Analog Output (Figure 1)
RL=200k, VEE=GND=0
Maximum Propagation Delay , Channel-Select
Input to Analog Output (Figure 1)
RL=200 k, VEE=GND=0
Maximum Propagation Delay , Channel-Select
Input to Analog Output
(Figure 2) RL=10 k
VEE=GND=0
VEE=-5В, GND=0
Maximum Propagation Delay , Enable to
Analog Output
(Figure 2) RL=10 k
VEE=GND=0
VEE=-10В, GND=0
Maximum Propagation Delay , Channel-Select
Input to Analog Output
(Figure 2) RL=10 k
VEE=GND=0
VEE=-5В, GND=0
Maximum Propagation Delay , Enable to
Analog Output
(Figure 2) RL=1,0 k
VEE=GND=0
VEE=-10В, GND=0
Maximum Input Capacitance, Channel-Select or
Enable Inputs
Maximum Capacitance
VEE=GND=-5V
CIS
COS
Feedthrough CIOS
5
10
15
5
10
15
5
10
15
5
5
10
15
5
5
10
15
5
5
10
15
5
-
5
5
5
Guaranteed Limit
-55 25 125
°C °C
°C
60 60 70
30 30 40
20 20 30
350 350 400
200 200 250
160 160 200
720 720 720
320 320 320
240 240 240
450 450 450
720 720 720
320 320 320
240 240 240
400 400 400
720 720 720
320 320 320
240 240 240
450 450 450
450 450 450
210 210 210
160 160 160
300 300 600
- 7.5 -
- 5* -
- 18* -
- 0.2* -
Unit
ns
ns
ns
ns
ns
ns
pF
pF
4

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KK4052B 전자부품, 판매, 대치품
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KK4052B
N SUFFIX PLASTIC
(MS - 001BB)
A
16 9
B
18
FL
C
-T- SEATING
PLANE
N
G KM
D
0.25 (0.010) M T
J
H
NOTES:
1. imensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
Symbol
A
B
C
D
F
G
H
J
K
L
M
N
Dimensions, mm
MIN
18.67
MAX
19.69
6.10 7.11
5.33
0.36 0.56
1.14 1.78
2.54
7.62
0° 10°
2.92 3.81
7.62 8.26
0.20 0.36
0.38
D SUFFIX SOIC
(MS - 012AC)
A
16 9
H BP
1G
8
C
-T-
D
SEATING
K PLANE
J
0.25 (0.010) M T C M
R x 45
F
M
NOTES:
1.Dimensions A and B do not include mold flash or protrusion.
2.Maximum mold flash or protrusion 0.15 mm (0.006) per side for A, for
B - 0.25 mm (0.010) per side.
Symbol.
A
B
C
D
F
G
H
J
K
M
P
R
Dimensions, mm
MIN
9.80
MAX
10.0
3.80 4.00
1.35 1.75
0.33 0.51
0.40 1.27
1.27
5.72
0° 8°
0.10 0.25
0.19 0.25
5.80 6.20
0.25 0.50
7

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부품번호상세설명 및 기능제조사
KK4052B

Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS

KODENSHI KOREA
KODENSHI KOREA

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