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9LPRS365 PDF 데이터시트 ( Data , Function )

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9LPRS365 데이터시트, 핀배열, 회로
Integrated
www.DataSheet4U.cCoimrcuit
Systems, Inc.
ICS9LPRS365
Advance Information
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
Recommended Application:
Pin Configuration
CK505 compliant clock with fully integrated voltage regulator
and Internal series resistor on differential outputs
Pin
Define
PCI0/CR#_A 1
VDDPCI 2
PCI1/CR#_B 3
64 SCLK
63 SDATA
62 REF0/FSLC/TEST_SEL
PCI2/TME 4
61 VDDREF
Output Features:
PCI3 5
60 X1
• 2 - CPU differential low power push-pull pairs
• 9 - SRC differential low power push-pull pairs
PCI4/27_Select 6
PCI_F5/ITP_EN 7
GNDPCI 8
59 X2
58 GNDREF
57 FSLB/TEST_MODE
• 1 - CPU/SRC selectable differential low power push-pull
pair
VDD48 9
USB_48MHz/FSLA 10
56 CK_PWRGD/PD#
55 VDDCPU
• 1 - SRC/DOT selectable differential low power push-pull
pair
GND48 11
VDD96_IO 12
SRCT0/DOTT_96 13
Top
View
54 CPUT0
53 CPUC0
52 GNDCPU
• 5 - PCI, 33MHz
SRCC0/DOTC_96 14
51 CPUT1_F
• 1 - PCI_F, 33MHz free running
• 1 - USB, 48MHz
GND 15
VDDPLL3 16
27MHz_NonSS/SRCT1/SE1 17
50 CPUC1_F
49 VDDCPU_IO
48 NC
• 1 - REF, 14.318MHz
27MHz_SS/SRCC1/SE2 18
47 CPUT2_ITP/SRCT8
GND 19
46 CPUC2_ITP/SRCC8
VDDPLL3_IO 20
45 VDDSRC_IO
Key Specifications:
SRCT2/SATAT 21
44 SRCT7/CR#_F
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
SRCC2/SATAC 22
GNDSRC 23
SRCT3/CR#_C 24
43 SRCC7/CR#_E
42 GNDSRC
41 SRCT6
• PCI outputs cycle-cycle jitter < 250ps
SRCC3/CR#_D 25
40 SRCC6
• +/- 100ppm frequency accuracy on CPU & SRC clocks
VDDSRC_IO 26
SRCT4 27
39 VDDSRC
38 PCI_STOP#
SRCC4 28
37 CPU_STOP#
Features/Benefits:
• Does not require external pass transistor for voltage
regulator
GNDSRC 29
SRCT9 30
SRCC9 31
SRCC11/CR#_G 32
36 VDDSRC_IO
35 SRCC10
34 SRCT10
33 SRCT11/CR#_H
• Integrated series resistors on differential outputs, Zo=50
64-TSSOP
• Supports spread spectrum modulation, default is 0.5%
down spread
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Selectable between one SRC differential push-pull pair
and two single-ended outputs
Table 1: CPU Frequency Select Table
FSLC2
B0b7
FSLB1
B0b6
FSLA1
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
00
0 266.66
00
1 133.33
01
01
0 200.00
1 166.66 100.00 33.33 14.318 48.00
10
0 333.33
10
1 100.00
11
11
0 400.00
1
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
1218—07/11/06
DOT
MHz
96.00
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.




9LPRS365 pdf, 반도체, 판매, 대치품
Integrated
www.DataSheet4UC.ciormcuit
Systems, Inc.
ICS9LPRS365
Advance Information
Pin Description (Continued)
PIN #
PIN NAME
33 SRCT11/CR#_H
34 SRCT10
35 SRCC10
36 VDDSRC_IO
37 CPU_STOP#
38 PCI_STOP#
39 VDDSRC
40 SRCC6
41 SRCT6
42 GNDSRC
43 SRCC7/CR#_E
44 SRCT7/CR#_F
45 VDDSRC_IO
46 CPUC2_ITP/SRCC8
47 CPUT2_ITP/SRCT8
48 NC
TYPE
I/O
OUT
OUT
PWR
IN
IN
PWR
OUT
OUT
PWR
I/O
I/O
PWR
OUT
OUT
N/A
DESCRIPTION
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request control of
SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair
must first be disabled in byte 3, bit 6 of SMBus configuration space After the SRC11 output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC10 pair using
byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
True clock of differential SRC clock pair.
Cpmplement clock of differential SRC clock pair.
1.05V to 3.3V from external power supply
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3 bits are
shifted in from the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted
in from the ICH to set the FSC, FSB, FSA values
VDD pin for SRC Pre-drivers, 3.3V nominal
Complement clock of low power differential SRC clock pair.
True clock of low power differential SRC clock pair.
Ground for SRC clocks
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request control of
SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair
must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte
6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of
SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair
must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte
6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
1.05V to 3.3V from external power supply
Complement clock of low power differential CPU2/Complement clock of differential SRC pair.
The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on
powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The function of
this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The
function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
No Connect
1218—07/11/06
4

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9LPRS365 전자부품, 판매, 대치품
Integrated
www.DataSheet4UC.ciormcuit
Systems, Inc.
Pin Description
PIN #
1 GNDREF
2 X2
3 X1
4 VDDREF
PIN NAME
5 REF0/FSLC/TEST_SEL
6 SDATA
7 SCLK
8 PCI0/CR#_A
9 VDDPCI
10 PCI1/CR#_B
11 PCI2/TME
12 PCI3
13 PCI4/27_Select
14 PCI_F5/ITP_EN
15 GNDPCI
16 VDD48
ICS9LPRS365
Advance Information
TYPE
PWR
OUT
IN
PWR
I/O
I/O
IN
I/O
PWR
I/O
I/O
OUT
I/O
I/O
PWR
PWR
DESCRIPTION
Ground pin for crystal oscillator circuit
Crystal output, nominally 14.318MHz.
Crystal input, Nominally 14.318MHz.
Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection.
Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level
latched input to enable test mode. Refer to Test Clarification Table.
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control
of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the
PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output
is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair
2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
Power supply pin for the PCI outputs, 3.3V nominal
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control
of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the
PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output
is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair
1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on
power-up as follows
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
3.3V PCI clock output.
3.3V PCI clock output / 27MH mode select for pin17, 18 strap. On powerup, the logic value on
this pin determines the power-up default of DOT_96/SRC0 and 27MHz/SRC1 output and the
function talbe for the pin17 and pin18.
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the
state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and
39 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
Ground for PCI clocks.
Power supply for USB clock, nominal 3.3V.
1218—07/11/06
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