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PDF PM6602 Data sheet ( Hoja de datos )
| Número de pieza | PM6602 | |
| Descripción | 8-row 30-mA LED driver | |
| Fabricantes | ST Microelectronics | |
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PM6602
8-row 30-mA LED driver with boost regulator, dual dimming mode,
SMBus interface and DPST for LCD panel backlights
Preliminary data
Features
■ 2 dimming modes: SMBus or PWM
■ Boost section
– 3.3 V to 28 V input voltage range
– Internal power MOSFET
– Internal +3.3 V LDO for device supply
– Up to 36 V output voltage
– Constant frequency peak current mode
control
– 500 kHz to 2 MHz adjustable switching
frequency
– Pulse-skip power saving mode at light
loads
– Built-in soft-start feature
– Programmable OVP protection
– Stable with ceramic output capacitors
– Thermal shutdown
■ Backlight driver section
– 8 rows with 30 mA maximum current
capability (adjustable)
– Row disabling option
– 500 ns minimum dimming time (1%
minimum dimming duty-cycle at 20 kHz)
– ±3% current accuracy
– ±2% current balance
– LED failure (open and short circuit)
detection
VFQFPN-24 4x4
AM03692v1
Description
The PM6602 consists of a high-efficiency
monolithic boost converter and eight controlled
current generators (ROWs), specifically designed
to supply LED arrays used in the backlights of
LCD panels. The device can manage a nominal
output voltage of up to 36 V. The generators can
be externally programmed to sink up to 30 mA
and they can be dimmed in two different modes:
via a PWM signal (1% dimming duty-cycle at 20
kHz can be managed) or in SMBus mode. The
device can detect and manage the open and
shorted LED faults. The device detects the
unused ROWs (connected to SGND). Basic
protections (output overvoltage, internal MOSFET
overcurrent and thermal shutdown) are provided.
Applications
■ Backlights of notebook monitors
■ Backlights of UMPC monitors
Table 1. Device summary
Part number
Package
PM6602
PM6602TR
VFQFPN-24 4 mm x 4 mm (exposed pad)
Packaging
Tube
Tape and reel
June 2009
Doc ID 15564 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/20
www.st.com
20
1 page  
www.DataSPhMee6t46U0.c2om
Device pinout
Table 2.
Pin #
22
23
24
Pin description (continued)
Name
Description
SCL SMBus clock
SDA SMBus data
DFSET
Dimming frequency selection in SMBus mode, using a rusticator to
SGND. Directly connect to SGND to setup the PWM dimming mode
Doc ID 15564 Rev 1
5/20
5 Page 
www.DataSPhMee6t46U0.c2om
5 SMBus interface
SMBus interface
The SMBus serial interface is used to turn on the device, monitor faults, set dimming mode
and brightness settings and configure the device in general.
The address is set to 0x58. No address pin is provided (compliant with DELL specifications),
nor any ROM address configuration.
Additional configuration bits and registers added for device configuration (other than those
specified in the DELL specification) include the shorted led threshold (2 bits).
The brightness control interface implements the SMBus read byte protocol.
The brightness control interface implements the SMBus write byte protocol.
The brightness control interface's SMBus component operates correctly when the SMBus
master clock operates at a frequency of 55 kHz.
The brightness control interface's SMBus component may use clock stretching, but it shall
not add more than 10 milliseconds of clock low time between any SMBus start condition and
its corresponding stop.
The brightness control interface sends a NAK signal (not acknowledge) in response to any
SMBus operation directed to it that does not use the SMBus read byte or write byte protocol.
The brightness control interface sends a NAK signal in response to any SMBus operation
directed to it that addresses a register that is not defined in this specification.
When the SMBus interface is not powered, the SMBus interface pins provide a high
impedance interface to the bus.
Read byte
As shown in Figure 4, the four-byte-long read byte protocol starts out with the slave address
followed by the "command code" which translates to the "register index". Then the bus
direction turns around with the re-broadcast of the slave address with bit 0 indicating a read
("Rd") cycle. The fourth byte contains the data being returned by the backlight controller.
That byte value in the data byte should reflect the value of the register being queried at the
"command code" index. A dark grey outline is used on cycles during which the backlight
controller "owns" or "drives" the data line. All other cycles are driven by the "host".
Figure 4. Read byte protocol
AM03642v1
Note that any other protocol missing the "command code" as implemented in some previous
backlight controller devices will no longer be supported.
Doc ID 15564 Rev 1
11/20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet PM6602.PDF ] | |
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