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기능 Numonyx Embedded Flash Memory
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Intel® Embedded Flash Memory (J3 v. D)
(32, 64, and 128 Mbit)
Datasheet
Product Features
Architecture
— High-density symmetrical 128-Kbyte
blocks
—128 Mbit (128 blocks)
—64 Mbit (64 blocks)
—32 Mbit (32 blocks)
Performance
— 75 ns Initial Access Speed (128/64/32
-Mbit densities)
— 25 ns 8-word and 4-word
Asynchronous page-mode reads
— 32-Byte Write buffer
—4 µs per Byte Effective
programming time
Security
— Enhanced security options for code
protection
— 128-bit Protection Register
—64-bit Unique device identifier
—64-bit User-programmable OTP cells
— Absolute protection with VPEN = GND
— Individual block locking
— Block erase/program lockout during
power transitions
Software
— Program and erase suspend support
— Flash Data Integrator (FDI), Common
Flash Interface (CFI) Compatible
System Voltage and Power
— VCC = 2.7 V to 3.6 V
— VCCQ = 2.7 V to 3.6 V
Quality and Reliability
— Operating temperature:
-40 °C to +85 °C
— 100K Minimum erase cycles per block
— 0.13 µm ETOX™ VIII Process
Packaging
— 56-Lead TSOP package
— 64-Ball Intel® Easy BGA package
The Intel® Embedded Flash Memory J3 Version D (J3 v. D) provides improved mainstream performance
with enhanced security features, taking advantage of the high quality and reliability of the NOR-based Intel
0.13 µm ETOX™ VIII process technology. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit
densities, the J3 v. D device brings reliable, low-voltage capability (3 V read, program, and erase) with high
speed, low-power operation.
The J3 v. D device takes advantage of the proven manufacturing experience and is ideal for code and data
applications where high density and low cost are required, such as in networking, telecommunications,
digital set top boxes, audio recording, and digital imaging.
Intel Flash Memory components also deliver a new generation of forward-compatible software support. By
using the Common Flash Interface (CFI) and Scalable Command Set (SCS), customers can take advantage
of density upgrades and optimized write capabilities of future Intel® Flash Memory devices.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the
latest datasheet before finalizing a design.
308551- 002
Sept 2005




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9.0 Flash Operations ...................................................................................................... 38
9.1 Status Register .................................................................................................... 38
9.1.1 Clearing the Status Register................................................................... 39
9.2 Read Operations ................................................................................................. 39
9.2.1 Read Array ............................................................................................. 39
9.2.2 Read Status Register ............................................................................. 40
9.2.3 Read Device Information ........................................................................ 40
9.2.4 CFI Query ............................................................................................... 41
9.3 Programming Operations .................................................................................... 41
9.3.1 Single-Word/Byte Programming ............................................................. 41
9.3.2 Buffered Programming ........................................................................... 42
9.4 Block Erase Operations....................................................................................... 43
9.5 Suspend and Resume ......................................................................................... 44
9.6 Status Signal (STS) ............................................................................................. 45
9.7 Security and Protection ....................................................................................... 46
9.7.1 Normal Block Locking............................................................................. 46
9.7.2 Configurable Block Locking .................................................................... 47
9.7.3 OTP Protection Registers....................................................................... 47
9.7.4 Reading the OTP Protection Register .................................................... 48
9.7.5 Programming the OTP Protection Register ............................................ 48
9.7.6 Locking the OTP Protection Register ..................................................... 48
9.7.7 VPP/ VPEN Protection ........................................................................... 50
Appendix A Device Command Codes ................................................................................. 51
Appendix B J3 v. D ID Codes .................................................................................................. 52
Appendix C
Flow Charts ........................................................................................................... 53
C.1 Write to Buffer...................................................................................................53
C.2 Status Register .................................................................................................54
C.3 Byte/Word Programming ..................................................................................55
C.4 Program Suspend/Resume ..............................................................................56
C.5 Block Erase.......................................................................................................57
C.6 Block Erase Suspend/Resume .........................................................................58
C.7 Block Locking....................................................................................................59
C.8 Unlock Block .....................................................................................................60
C.9 OTP Protection Register Programming ............................................................61
Appendix D
Common Flash Interface ................................................................................. 62
D.2 Query Structure Overview ................................................................................63
D.3 Block Status Register .......................................................................................64
D.4 CFI Query Identification String..........................................................................64
D.5 System Interface Information............................................................................65
D.6 Device Geometry Definition ..............................................................................66
D.7 Primary-Vendor Specific Extended Query Table ..............................................67
Appendix E Additional Information...................................................................................... 69
Appendix F Ordering Information......................................................................................... 70
4 Datasheet

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Word:
Kword:
Kb:
KB:
Mb:
MB:
Brackets:
00FFh:
00FF 00FFh:
DQ[15:0]:
16 bits
1,024 words
1,024 bits
1,024 bytes
1,048,576 bits
1,048,576 bytes
Square brackets ([]) will be used to designate group membership or to define a
group of signals with similar function (i.e. A[21:1], SR[4,1] and D[15:0]).
Denotes 16-bit hexadecimal numbers
Denotes 32-bit hexadecimal numbers
Data I/O signals
Datasheet
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Numonyx Embedded Flash Memory

Intel Corporation
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