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PDF CXA3685ER Data sheet ( Hoja de datos )
| Número de pieza | CXA3685ER | |
| Descripción | Direct Conversion IC | |
| Fabricantes | Sony Corporation | |
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Direct Conversion IC for Digital Satellite Broadcast Tuner
CXA3685ER
Description
The CXA3685ER is an IC developed for direct orthogonal detection of L band (1 to 2GHz) IF signals in a digital
satellite broadcast reception tuner.
This direct conversion (Zero-IF) technology eliminates the need for the SAW filter that was formerly necessary.
In addition, the CXA3685ER incorporates an RF gain control amplifier, oscillator circuit, wide-band phase
shifter circuit and other RF circuits, a baseband LPF, baseband gain control amplifier, tuning PLL, and the
inductor and varactor diode needed for a tuning VCO. This makes it possible to realize the front-end RF block
without tuning the RF circuits.
(Applications: BS/CS digital broadcast (ISDB-S) tuner)
Features
Low power consumption: 430mW (typ.)
No need for an external inductor and varactor diode
3.3V single power supply
Reception frequency: 950MHz to 2150MHz
Wide input range (typ. –65dBm to –15dBm)
Internal wide band 90° phase shifter
Internal output for controlling an external attenuator
Reference signal output for the demodulation circuit
Enables to use external reference signals
Small package: 48-pin VQFN
Enables to reduce power consumption in power save mode when not used: 180mW (typ.)
Package
48-pin VQFN (Plastic)
Note) This IC has pins whose electrostatic discharge strength is weak as the high-frequency process is used. Take care of
handling the IC.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E06X01-CR
1 page  
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Pin No.
Symbol
Pin voltage [V]
Equivalent circuit
AVCC
10
1k
7 AGC
8, 13,
18
AGND
0 to 3.3
0
500
7
8
13
AGND
18
1k 1k
4k
9 REFCLOCK
—
10 AVCC
3.3
DVCC
31
500
9
140k
5k
32
DGND
45k
DVCC
31
11 LD
0 or 3.3
11
CXA3685ER
Description
AGC control voltage input
GND for the mixer and baseband
circuit
Frequency change for the
reference signal output
(See page 19.)
Power supply for the mixer and
baseband circuit
PLL lock detection
12 NC
14 QOUT
17 IOUT
32
DGND
—
1.6
1.6
AVCC
10
17 14
10k 2k
18 13 8
AGND
Not used
Baseband signal output
-5-
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Register Block
Item
Symbol Measurement conditions
Bus timing (I2C bus)
SCL clock frequency
fSCL
Bus free time between “STOP”
condition and “STOP” condition
tBUF
Start-Hold time
tH; STA
Low hold time
tLOW
High hold time
tHIGH
Start-Setup time
tS; STA
Data-Hold time
tH; DAT
Data-Setup time
tS; DAT
Rise time
tR
Fall time
tF
Stop-Setup time
tS; STO
Capacitive load of bus line
Cb
Min.
0
1300
600
1300
600
600
0
100
600
I2C Bus Timing Chart
Typ.
CXA3685ER
Max. Unit
400 kHz
ns
ns
ns
ns
ns
900 ns
ns
300 ns
300 ns
ns
400 pF
SDA
tBUF
tS; STA
tR tF
tS; STO
SCL
tH; STA
tLOW
tHIGH
tS; DAT
tH; DAT
START
CLOCK
DATA CHANGE
tBUF= Bus free time
tW; STA= Start waiting time
tH; STA= Start hold time
tLOW= Low clock pulse width
tHIGH= High clock pulse width
tS; DAT= Data setup time
tH; DAT= Data hold time
tS; STO= Stop setup time
tR= Rise time
tF= Fall time
STOP
- 11 -
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet CXA3685ER.PDF ] | |
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