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Analog Devices에서 제조한 전자 부품 ADCLK950은 전자 산업 및 응용 분야에서
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부품번호 ADCLK950 기능
기능 SiGe Clock Fanout Buffer
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ADCLK950 데이터시트, 핀배열, 회로
Data Sheet
Two Selectable Inputs, 10 LVPECL Outputs,
SiGe Clock Fanout Buffer
ADCLK950
FEATURES
2 selectable differential inputs
4.8 GHz operating frequency
75 fs rms broadband random jitter
On-chip input terminations
3.3 V power supply
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK950 is an ultrafast clock fanout buffer fabricated
on the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The device has two selectable differential inputs via the IN_SEL
control pin. Both inputs are equipped with center tapped,
differential, 100 Ω on-chip termination resistors. The inputs
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A
VREFx pin is available for biasing ac-coupled inputs.
The ADCLK950 features 10 full-swing emitter coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The output stages are designed to directly drive 800 mV each
side into 50 Ω terminated to VCC − 2 V for a total differential
output swing of 1.6 V.
The ADCLK950 is available in a 40-lead LFCSP and specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
ADCLK950
LVPECL
Q0
Q0
Q1
Q1
Q2
Q2
VREF0
REFERENCE
Q3
Q3
VT0
CLK0
CLK0
VT1
CLK1
CLK1
Q4
Q4
Q5
Q5
Q6
Q6
IN_SEL
Q7
Q7
VREF1
REFERENCE
Q8
Q8
Q9
Q9
Figure 1.
Rev. B
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADCLK950 pdf, 반도체, 판매, 대치품
Data Sheet
ADCLK950
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (Typ column) values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (Min column) and maximum
(Max column) values are given over the full VCC − VEE = 3.3 V ± 10% and TA = −40°C to +85°C variation, unless otherwise noted.
Table 1. Clock Inputs and Outputs
Parameter
Symbol Min Typ Max Unit Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input Common Mode Voltage
Input Differential Range
Input Capacitance
Input Resistance
Single-Ended Mode
Differential Mode
Common Mode
Input Bias Current
Hysteresis
VICM
VID
CIN
VEE + 1.5
0.4
0.4
50
100
50
20
10
VCC − 0.1
3.4
V
V p-p
pF
±1.7 V between input pins
kΩ Open VTx
µA
mV
DC OUTPUT CHARACTERISTICS
Output Voltage High Level
Output Voltage Low Level
Output Voltage, Single Ended
Reference Voltage
Output Voltage
Output Resistance
VOH
VOL
VO
VREF
VCC − 1.26
VCC − 1.99
610
VCC − 0.76
VCC − 1.54
960
V
V
mV
(VCC + 1)/2
235
V
50 Ω to (VCC − 2.0 V)
50 Ω to (VCC − 2.0 V)
VOH − VOL, output static
−500 µA to +500 µA
Table 2. Timing Characteristics
Parameter
Symbol
AC PERFORMANCE
Maximum Output Frequency
Min
4.5
Output Rise Time
Output Fall Time
Propagation Delay
Temperature Coefficient
Output-to-Output Skew1
Part-to-Part Skew
Additive Time Jitter
Integrated Random Jitter
Broadband Random Jitter2
Crosstalk-Induced Jitter3
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise
tR
tF
tPD
40
40
175
fIN = 1 GHz
Typ Max
4.8
75 90
75 90
210 245
50
9 28
45
28
75
90
−119
−134
−145
−150
−150
Unit Test Conditions/Comments
GHz
ps
ps
ps
fs/°C
ps
ps
fs rms
fs rms
fs rms
See Figure 4 for differential output voltage vs.
frequency, >0.8 V differential output swing
20% to 80% measured differentially
VICM = 2 V, VID = 1.6 V p-p
VID = 1.6 V p-p
BW = 12 kHz − 20 MHz, CLK = 1 GHz
VID = 1.6 V p-p, 8 V/ns, VICM = 2 V
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns (see Figure 11, the
phase noise plot, for more details)
@100 Hz offset
@1 kHz offset
@10 kHz offset
@100 kHz offset
>1 MHz offset
1 The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
2 Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
3 This is the amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs.
Rev. B | Page 3 of 12

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ADCLK950 전자부품, 판매, 대치품
ADCLK950
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
IN_SEL 1
CLK0 2
CLK0 3
VREF0 4
VT0 5
CLK1 6
CLK1 7
VT1 8
VREF1 9
VEE 10
ADCLK950
TOP VIEW
(Not to Scale)
30 VCC
29 NC
28 NC
27 Q4
26 Q4
25 Q5
24 Q5
23 NC
22 NC
21 VCC
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EPAD MUST BE SOLDERED TO THE VEE POWER PLANE.
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic Description
1
IN_SEL
Input Select. Logic 0 selects CLK0 and CLK0 inputs. Logic 1 selects CLK1 and CLK1 inputs.
2
CLK0
Differential Input (Positive) 0.
3
CLK0
Differential Input (Negative) 0.
4
VREF0
Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and CLK0 inputs.
5 VT0 Center Tap. Center tap of a 100 Ω input resistor for CLK0 and CLK0 inputs.
6
CLK1
Differential Input (Positive) 1.
7
CLK1
Differential Input (Negative) 1.
8
9
10
11, 20, 21,
30, 31, 40
VT1
VREF1
VEE
VCC
Center Tap. Center tap of a 100 Ω input resistor for CLK1 and CLK1 inputs.
Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and CLK1 inputs.
Negative Supply Pin.
Positive Supply Pin.
12, 13
Q9, Q9
Differential LVPECL Outputs.
14, 15
Q8, Q8
Differential LVPECL Outputs.
16, 17
Q7, Q7
Differential LVPECL Outputs.
18, 19
Q6, Q6
Differential LVPECL Outputs.
22, 23, 28, NC
29
No Connection
24, 25
Q5, Q5
Differential LVPECL Outputs.
26, 27
Q4, Q4
Differential LVPECL Outputs.
32, 33
Q3, Q3
Differential LVPECL Outputs.
34, 35
Q2, Q2
Differential LVPECL Outputs.
36, 37
Q1, Q1
Differential LVPECL Outputs.
38, 39
Q0, Q0
Differential LVPECL Outputs.
EPAD
Exposed Pad. The EPAD must be soldered to the VEE power plane.
Rev. B | Page 6 of 12

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