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부품번호 | AD5722 기능 |
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기능 | (AD57x2) Voltage Output DACs | ||
제조업체 | Analog Devices | ||
로고 | |||
전체 30 페이지수
www.DataSheet4U.com
Complete, Dual, 12-/14-/16-Bit, Serial
Input, Unipolar/Bipolar, Voltage Output DACs
AD5722/AD5732/AD5752
FEATURES
Complete, dual, 12-/14-/16-bit digital-to-analog converter (DAC)
Operates from single/dual supplies
Software programmable output range
+5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V
INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum
Total unadjusted error (TUE): 0.1% FSR maximum
Settling time: 10 µs typical
Integrated reference buffers
Output control during power-up/brownout
Simultaneous updating via LDAC
Asynchronous CLR to zero scale or midscale
DSP-/microcontroller-compatible serial interface
24-lead TSSOP
Operating temperature range: −40°C to +85°C
iCMOS process technology1
APPLICATIONS
Industrial automation
Closed-loop servo control, process control
Automotive test and measurement
Programmable logic controllers
GENERAL DESCRIPTION
The AD5722/AD5732/AD5752 are dual, 12-/14-/16-bit, serial
input, voltage output, digital-to-analog converters. They operate
from single-supply voltages from +4.5 V up to +16.5 V or dual-
supply voltages from ±4.5 V up to ±16.5 V. Nominal full-scale
output range is software-selectable from +5 V, +10 V, +10.8 V,
±5 V, ±10 V, or ±10.8 V. Integrated output amplifiers, reference
buffers, and proprietary power-up/power-down control circuitry
are also provided.
The parts offer guaranteed monotonicity, integral nonlinearity
(INL) of ±16 LSB maximum, low noise, and 10 µs typical
settling time.
The AD5722/AD5732/AD5752 use a serial interface that
operates at clock rates up to 30 MHz and are compatible with
DSP and microcontroller interface standards. Double buffering
allows the simultaneous updating of all DACs. The input coding
is user-selectable twos complement or offset binary for a bipolar
output (depending on the state of Pin BIN/2sComp), and
straight binary for a unipolar output. The asynchronous clear
function clears all DAC registers to a user-selectable zero-scale
or midscale output. The parts are available in a 24-lead TSSOP
and offer guaranteed specifications over the −40°C to +85°C
industrial temperature range.
The AD5722/AD5732/AD5752 are pin compatible with the
AD5724/AD5734/AD5754, which are complete, quad, 12-/14-/
16-bit, serial input, unipolar/bipolar voltage output DACs.
FUNCTIONAL BLOCK DIAGRAM
AVSS AVDD
REFIN
DVCC
CLR
BIN/2sCOMP
SDIN
SCLK
SYNC
SDO
AD5722/AD5732/AD5752
REFERENCE
BUFFERS
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
12/14/16
INPUT
REGISTER A
DAC
12/14/16
REGISTER A
DAC A
INPUT
REGISTER B
DAC
12/14/16
REGISTER B
DAC B
VOUTA
VOUTB
GND
LDAC
Figure 1.
DAC_GND (2) SIG_GND (2)
1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS® is a technology
platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and
package size, as well as increased ac and dc performance.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD5722/AD5732/AD5752
www.DataSheet4U.com
Parameter
DIGITAL INPUTS3
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current
Pin Capacitance
DIGITAL OUTPUTS (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage
Current
High Impedance Output
Capacitance
POWER REQUIREMENTS
AVDD
AVSS
DVCC
Power Supply Sensitivity3
∆VOUT/∆ΑVDD
AIDD
AISS
DICC
Power Dissipation
Power-Down Currents
AIDD
AISS
DICC
Min Typ Max
2
0.8
±1
5
DVCC − 1
DVCC − 0.5
−1
5
0.4
0.4
+1
Unit
V
V
µA
pF
V
V
V
V
µA
pF
4.5 16.5 V
−4.5 −16.5 V
2.7 5.5 V
−65
3.25
2.4
2.5
0.5 3
190
79
dB
mA/channel
mA/channel
mA/channel
µA
mW
mW
40 µA
40 µA
300 nA
Test Conditions/Comments
DVCC = 2.7 V to 5.5 V, JEDEC compliant
Per pin
Per pin
DVCC = 5 V ± 10%, sinking 200 µA
DVCC = 5 V ± 10%, sourcing 200 µA
DVCC = 2.7 V to 3.6 V, sinking 200 µA
DVCC = 2.7 V to 3.6 V, sourcing 200 µA
Outputs unloaded
AVSS = 0 V, outputs unloaded
Outputs unloaded
VIH = DVCC, VIL = GND
±16.5 V operation, outputs unloaded
16.5 V operation, AVSS = 0 V, outputs unloaded
1 For specified performance, the maximum headroom requirement is 0.9 V.
2 INL is the relative accuracy. It is measured from Code 512, Code 128, and Code 32 for the AD5752, the AD5732, and the AD5722, respectively.
3 Guaranteed by characterization; not production tested.
Rev. 0 | Page 4 of 32
4페이지 www.DataSheet4U.com
SCLK
SYNC
SDIN
SDO
AD5722/AD5732/AD5752
1 24 1 24
t17
DB23
DB0
DB23
DB0
DB23
INPUT WORD SPECIFIES
REGISTER TO BE READ
DB0
DB23
NOP CONDITION
DB0
UNDEFINED
Figure 4. Readback Timing Diagram
SELECTED REGISTER DATA
CLOCKED OUT
Rev. 0 | Page 7 of 32
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