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PDF PO74HSTL85350A Data sheet ( Hoja de datos )
| Número de pieza | PO74HSTL85350A | |
| Descripción | LVCMOS Input to HSTL Output 1:4 Fanout Buffer | |
| Fabricantes | Potato Semiconductor Corporation | |
| Logotipo |  |
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PO74HSTL85350A
LVCMOS Input to HSTL Output 1:4 Fanout Buffer
300MHz HSTL Potato Chip
03/24/07
FEATURES:
. Patented Technology
. Four HSTL differential outputs
. Two single LVTTL/LVCMOS inputs
. Operating frequency up to 300MHz with 15 pf load
. Very low output pin to pin skew < 50ps
. 3.4-ns propagation delay (max)
. 2.4V to 3.6V power supply
. Industrial temperature range: –40°C to 85°C
. 20-pin TSSOP package
DESCRIPTION:
The PO74HSTL85350A is a low-skew, 1-to-4 differential
fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications.
The device is implemented on CMOS technology and has
a fully differential internal architecture that is optimized to
achieve low signal skews at operating frequencies of up to
300MHz .
The device features two single-ended input paths that are
multiplexed internally. This mux is controlled by the
CLK_SEL pin. The PO74HSTL85350A functions as a
signal-level translator and fanout on LVCMOS / LVTTL
single-ended signal to four HSTL differential loads. Since
the PO74HSTL85350A introduces negligible jitter to the
timing budget, it is the ideal choice for distributing high
frequency, high precision clocks across back-planes and
boards in communication systems.
Pin Configuration
VEE
CLK_EN
CLK_SEL
CLK0
nc
CLK1
nc
nc
nc
VCC
1
2
3
4
5
6
7
8
9
10
20 Q0
19 nQ0
18 VCC
17 Q1
16 nQ1
15 Q2
14 nQ2
13 VCC
12 Q3
11 nQ3
Logic Block Diagram
CLK_EN
CLK0
CLK1
CLK_SEL
0
1
D
Q
LE
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
1
Copyright © Potato Semiconductor Corporation
1 page  
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PO74HSTL85350A
LVCMOS Input to HSTL Output 1:4 Fanout Buffer
300MHz HSTL Potato Chip
03/24/07
Test Waveforms
FIGURE 1.
LVTTL/LVCMOS INPUT WAVEFORM DEFINITION
Input
FIGURE 2.
HSTL OUTPUT
3V
1.5V
0V
tr,tf,
20-80%
VO
FIGURE 3.
Propogation Delay, Output pulse skew, and output-to-output skew for D to output pair
INPUT
CLOCK
OUTPUT
CLOCK
TPLH
TPD
ANOTHER
OUTPUT
CLOCK
TPHL
tSK(O)
VO
FIGURE 4.
CLK_EN Timing Diagram
Disabled
CLK
CLK_EN
Enabled
nQ0:nQ3
Q0:Q3
5
Copyright © Potato Semiconductor Corporation
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PO74HSTL85350A.PDF ] | |
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