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74AUP2G79 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 74AUP2G79은 전자 산업 및 응용 분야에서
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부품번호 74AUP2G79 기능
기능 Low-power dual D-type flip-flop
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74AUP2G79 데이터시트, 핀배열, 회로
www.DataSheet4U.com
74AUP2G79
Low-power dual D-type flip-flop; positive-edge trigger
Rev. 02 — 19 March 2008
Product data sheet
1. General description
The 74AUP2G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on
the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the
clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
2. Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101-C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from 40 °C to +85 °C and 40 °C to +125 °C




74AUP2G79 pdf, 반도체, 판매, 대치품
www.DNatXaSPheSete4Um.coicmonductors
74AUP2G79
Low-power dual D-type flip-flop; positive-edge trigger
7. Functional description
Table 4.
Input
nCP
L
Function table[1]
nD
L
H
X
Output
nQ
L
H
q
[1] H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
VI
IOK
VO
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0 V
VO > VCC or VO < 0 V
Active mode and Power-down mode
VO = 0 V to VCC
Tamb = 40 °C to +125 °C
0.5
-
[1] 0.5
-
[1] 0.5
-
-
-
65
[2] -
+4.6
50
+4.6
±50
+4.6
±20
50
50
+150
250
V
mA
V
mA
V
mA
mA
mA
°C
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 and XQFN8U packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC
VI
VO
Operating conditions
Parameter
supply voltage
input voltage
output voltage
Tamb
t/V
ambient temperature
input transition rise and fall rate
Conditions
Active mode
Power-down mode; VCC = 0 V
VCC = 0.8 V to 3.6 V
Min Max Unit
0.8 3.6 V
0 3.6 V
0
VCC
V
0 3.6 V
40
+125
°C
0 200 ns/V
74AUP2G79_2
Product data sheet
Rev. 02 — 19 March 2008
© NXP B.V. 2008. All rights reserved.
4 of 19

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74AUP2G79 전자부품, 판매, 대치품
www.DNatXaSPheSete4Um.coicmonductors
74AUP2G79
Low-power dual D-type flip-flop; positive-edge trigger
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Typ
Tamb = 40 °C to +125 °C
VIH HIGH-level input voltage
VCC = 0.8 V
VCC = 0.9 V to 1.95 V
0.75 × VCC -
0.70 × VCC -
VCC = 2.3 V to 2.7 V
1.6 -
VCC = 3.0 V to 3.6 V
2.0 -
VIL LOW-level input voltage VCC = 0.8 V
--
VCC = 0.9 V to 1.95 V
--
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
--
--
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VCC 0.11 -
0.6 × VCC -
0.93 -
1.17 -
1.77 -
1.67 -
2.40 -
2.30 -
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
-
-
IO = 1.1 mA; VCC = 1.1 V
--
IO = 1.7 mA; VCC = 1.4 V
--
IO = 1.9 mA; VCC = 1.65 V
--
IO = 2.3 mA; VCC = 2.3 V
--
IO = 3.1 mA; VCC = 2.3 V
--
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
--
--
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
IOFF
IOFF
power-off leakage current
additional power-off
leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
-
-
ICC
ICC
supply current
additional supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
per pin; VI = VCC 0.6 V; IO = 0 A;
VCC = 3.3 V
-
[1] -
-
-
[1] One input at VCC 0.6 V, other input at VCC or GND.
Max Unit
-V
-V
-V
-V
0.25 × VCC V
0.30 × VCC V
0.7 V
0.9 V
-V
-V
-V
-V
-V
-V
-V
-V
0.11 V
0.33 × VCC V
0.41 V
0.39 V
0.36 V
0.50 V
0.36 V
0.50 V
±0.75
µA
±0.75
µA
±0.75
µA
1.4 µA
75 µA
74AUP2G79_2
Product data sheet
Rev. 02 — 19 March 2008
© NXP B.V. 2008. All rights reserved.
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74AUP2G79

Low-power dual D-type flip-flop

NXP Semiconductors
NXP Semiconductors

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