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PDF IT8780F Data sheet ( Hoja de datos )

Número de pieza IT8780F
Descripción Serverwork I/o
Fabricantes Integrated Technology Express　
Logotipo Integrated Technology Express Logotipo



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IT8780F
ServerWork I/O
(Code Name: SWIO)
Preliminary Specification V0.3
INTEGRATED TECHNOLOGY EXPRESS, INC.
Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact
sales representatives.

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IT8780F
8.11.4 Programmable Chip Select 2 Base Address LSB Register (Index=63h, Default=00h) .......58
8.11.5 GPIO(W) Set 1, 2, 3, 4, 5, and 6 Pin Polarity Registers (Index=B0h, B1h, B2h, B3h, B4h,
and B5h, Default=00h) .....................................................................................................58
8.11.6 GPIO(W) Set 1, 2, 3, 4, 5, and 6 Pin Internal Pull-up Enable Registers (Index=B8h, B9h,
BAh, BBh, BCh, and BDh, Default=00h) ...........................................................................58
8.11.7 Simple I/O Set 1, 2, 3, 4, 5, and 6 Data Registers (Index=C0h, C1h, C2h, C3h, C4h, and
C5h, Default=00h) ............................................................................................................58
8.11.8 Simple I/O Set 1, 2, 3, 4, 5, and 6 Input/Output Selection Registers (Index=C8h, C9h, CAh,
CBh, CCh, and CDh, Default=00h) ...................................................................................58
8.11.9 IRQ3-7, 9-12 and 14-15 External Routing Input Pin Mapping Registers (Index=E3h-E7h,
E9h-ECh and EEh-EFh, Default=00h) ..............................................................................59
8.11.10 Programmable Chip Select Configuration Registers (Index=F0h, Default=00h) .................59
8.11.11 User-defined Memory Base Address High Byte Register (Index=F1h, Default=00h)..........59
8.11.12 User-defined Memory Base Address Low Byte Register (Index=F2h, Default=00h)...........59
8.11.13 User-defined Memory Size High Byte Register (Index=F3h, Default=00h).........................60
8.11.14 User-defined Memory Size Low Byte Register (Index=F4h, Default=00h) .........................60
8.12 RTC Configuration Registers (LDN=08h) ......................................................................................61
8.12.1 RTC Activate (Index=30h, Default=00h or 01h).................................................................61
8.12.2 RTC Primary Base Address MSB Register (Index=60h, Default=00h) ................................61
8.12.3 RTC Primary Base Address LSB Register (Index=61h, Default=70h) .................................61
8.12.4 RTC Secondary Base Address MSB Register (Index=62h, Default=00h)............................61
8.12.5 RTC Secondary Base Address LSB Register (Index=63h, Default=72h).............................61
8.12.6 RTC Interrupt Level Select (Index=70h, Default=08h) .......................................................61
8.12.7 RTC Interrupt Type (Index=71h, Default=02h) ..................................................................62
8.12.8 RTC Special Configuration Register (Index=F0h, Default=00h).........................................62
9. Functional Description ............................................................................................................................65
9.1 LPC Interface ...............................................................................................................................65
9.1.1 LPC Transactions.............................................................................................................65
9.1.2 LDRQ# Encoding .............................................................................................................65
9.2 Serialized IRQ ..............................................................................................................................65
9.2.1 Continuous Mode .............................................................................................................65
9.2.2 Quiet Mode ......................................................................................................................66
9.2.3 Waveform Samples of SERIRQ Sequence .......................................................................66
9.2.4 SERIRQ Sampling Slot ....................................................................................................67
9.3 General Purpose I/O ....................................................................................................................68
9.3.1 Serial Bus ........................................................................................................................69
9.3.2 The Extended Interface ....................................................................................................69
9.3.2.1 The Flash ROM I/F and the User-defined Memory Extension ...............................69
9.3.2.2 The Programmable Chip Selects Extension..........................................................70
9.4 System Wake-up Control (SWC) and ACPI ..................................................................................71
9.4.1 SWC General Description ................................................................................................71
9.4.2 ACPI Registers ................................................................................................................72
9.4.2.1 PM1 Status Block b Low Register (PM1b_STS_LOW)..........................................72
9.4.2.2 PM1 Status Block b High Register (PM1b_STS_HIGH) ........................................73
9.4.2.3 PM1 Enable Block b Low Register (PM1b_EN_LOW)...........................................73
9.4.2.4 PM1 Enable Block b High Register (PM1b_EN_ HIGH) ........................................74
9.4.2.5 PM1 Control Block b Low Register (PM1b_ CNT _LOW) ......................................74
9.4.2.6 PM1 Control Block b High Register (PM1b_ CNT _HIGH) ....................................74
9.4.2.7 General Purpose 1 Status 0 Register (GPE1_STS_0) ..........................................75
9.4.2.8 General Purpose 1 Status 1 Register (GPE1_STS_1) ..........................................75
9.4.2.9 General Purpose 1 Status 2 Register (GPE1_STS_2) ..........................................75
9.4.2.10 General Purpose 1 Status 3 Register (GPE1_STS_3) ..........................................77
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