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PDF STA2064 Data sheet ( Hoja de datos )
| Número de pieza | STA2064 | |
| Descripción | infotainment application processor | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STA2064
Cartesio™ family
infotainment application processor with embedded GPS
Data brief
Features
■ ARM1176 533 MHz host processor
– Cache: 32 KB instruction, 32 KB data
– Vector floating point unit
■ High performance embedded GPS subsystem
– Parallel acquisition engines for 8 GPS
satellites or 4 Galileo satellites
– 32 tracking channels for all satellites in view
– 5 correlators per channel for urban canyon
robustness
– Multibit signal processing hardware
■ Advanced power management
– Separated power islands for ultra low
power mode
– Dynamic core frequency scaling
– 512-Byte embedded SRAM for back-up
■ System infrastructure
– LP DDR/DDR2 controller: 16 bit data
512 MB addressable. (333 MHz DDR2,
200 MHz LPDDR)
– One bank of 32 KB embedded SRAM
– 64-channel vector interrupt controller (VIC)
– 2 DMA controllers, 16 physical channels
– 32 DMA request for each controller
– Two external DMA requests are supported
■ Display and graphics
– Color LCD controller for STN,TFT or HR-
TFT panels with 18-bit parallel RGB
interface
– Integrated touch screen controller and ADC
– 3D advanced graphics acceleration
– JPEG baseline profile decoder
■ High throuput interfaces
– 1 port USB 2.0 OTG with integrated
physical layer
– 2 SD/MMC, both bootable
■ Audio interfaces and features
– Three multichannel serial ports (I2S/TDM)
– SPDIF input interface
TFBGA289 (15x15x1.2mm)
– C3 hardware reed-solomon decoder
– Sample rate converter
■ Standard interfaces
– Three 16-bit input capture/output compare
– Pulse width light modulator (PWL)
– Three autobaud UART
– Three I2C multimaster/slave interfaces
– Two synchronous serial port (SSP, SPI)
– Five 32-bit GPIO ports
■ One controller area network (CAN) in
automotive version
■ Programmable voltage IOs: 1.8 V, 2.5 V, 3.3 V
■ VIOON: 1.8 ±10%V, VDDON: VDD, 1.0 ±10%V
■ TFBGA 289, 0.8 mm pitch package, packing in
tray
■ Ambient temperature range: -40 / +85 °C
Table 1. Device summary
Order code
Qualification
grade
CPU freq.
STA2064N Consumer 533 MHz
STA2064A Automotive 533 MHz
CAN
No
1x
July 2009
Doc ID 16057 Rev 1
For further information contact your local STMicroelectronics sales office.
1/19
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2 System description
System description
2.1 MCU
ARM1176-JZF advanced risc machine CPU up to 533 MHz (with Vdd greater or equal to
1.20 V and under process and temperature worst case conditions).
2.2
2.2.1
Embedded memories
Embedded SRAM (eSRAM)
The embedded SRAM is 8K x 32 (32 KB).
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
System functions
System and reset controller (SRC)
This provides a control interface for clock generation components external to the subsystem.
It also controls system-wide and peripherals-specific energy management features.
PMU
The power manager module controls the SLEEP to DEEP-SLEEP modes transition,
controls the external voltage switches on the Vdd and Vddio, monitors the external power
supply (via two signals, Vddok and BATOK), can force the emergency entry of the SDRAM
in self-refresh, and controls the wake-up from DEEP-SLEEP mode.
DMA
Direct memory access can be used with DMA peripherals. FIFO fill/empty requests from
these peripherals can be serviced immediately by the DMA Controller without CPU
interaction. Peripheral-to-peripheral and memory-to-memory DMA are also supported.
STA2064 features two DMA engines. Each DMA supports up to 8-channels and up to 32
requests.
Vectored interrupt controller (VIC)
The VIC allows the OS interrupt handler to quickly dispatch interrupt service routines in
response to peripheral interrupts.
GPIOs
Four GPIO ports provide 65 programmable inputs or outputs that can be controlled in two
modes:
● software mode through an APB bus interface
● hardware mode through a hardware control interface
Doc ID 16057 Rev 1
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5 Page 
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System description
2.7.4
Driving strength and slew rate programmability
The IO Driving Strength is programmable for the following interfaces as follows:
● SD/MMC0 (4, 6, 8 mA)
(default 8mA)
● SD/MMC1 (4, 6, 8 mA)
(default 8mA)
● LCD
(4, 8 mA)
(default 8mA)
● DRAM
(weak 70Ω, strong 50Ω) (default strong, 50Ω)
The Slew Rate is also controllable for the following interface as follows:
● SD/MMC0 (Nominal, Fast)
(default Nominal slew rate)
● SD/MMC1 (Nominal, Fast)
(default Nominal slew rate)
● LCD
(Nominal, Fast)
(default Fast slew rate)
● DRAM
(200, 266, 333 MHz)
(default 200 MHz)
● MSP0
(Nominal, Fast)
(default Nominal slew rate)
● MSP1
(Nominal, Fast)
(default Nominal slew rate)
Doc ID 16057 Rev 1
11/19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet STA2064.PDF ] | |
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