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PDF BUK954R2-55B Data sheet ( Hoja de datos )
| Número de pieza | BUK954R2-55B | |
| Descripción | TrenchMOS logic level FET | |
| Fabricantes | NXP Semiconductors | |
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BUK95/964R2-55B
TrenchMOS™ logic level FET
Rev. 02 — 8 October 2002
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect power transistor in a plastic package using
Philips High-Performance Automotive TrenchMOS™ technology.
Product availability:
BUK954R2-55B in SOT78 (TO-220AB)
BUK964R2-55B in SOT404 (D2-PAK).
1.2 Features
s Very low on-state resistance
s 175 °C rated
s Q101 compliant
s Logic level compatible.
1.3 Applications
s Automotive systems
s Motors, lamps and solenoids
s 12 V and 24 V loads
s General purpose power switching.
1.4 Quick reference data
s EDS(AL)S ≤ 1.2 J
s ID ≤ 75 A
s RDSon = 3.5 mΩ (typ)
s Ptot ≤ 300 W.
2. Pinning information
Table 1: Pinning - SOT78 and SOT404 simplified outlines and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d)
[1]
mb
mb
3 source (s)
mb mounting base,
connected to
drain (d)
MBK106
123
SOT78 (TO-220AB)
2
1 3 MBK116
SOT404 (D2-PAK)
[1] It is not possible to make connection to pin 2 of the SOT404 package.
Symbol
d
g
MBB076
s
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Philips Semiconductors
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BUK95/964R2-55B
TrenchMOS™ logic level FET
5. Characteristics
Table 4: Characteristics
Tj = 25 °C unless otherwise specified
Symbol Parameter
Conditions
Static characteristics
V(BR)DSS
VGS(th)
drain-source breakdown
voltage
ID = 0.25 mA; VGS = 0 V
Tj = 25 °C
Tj = −55 °C
gate-source threshold voltage ID = 1 mA; VDS = VGS;
Figure 9
IDSS
IGSS
RDSon
drain-source leakage current
gate-source leakage current
drain-source on-state
resistance
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
VDS = 55 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±15 V; VDS = 0 V
VGS = 5 V; ID = 25 A;
Figure 7 and 8
Dynamic characteristics
Tj = 25 °C
Tj = 175 °C
VGS = 4.5 V; ID = 25 A
VGS = 10 V; ID = 25 A
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
Ld
total gate charge
gate-to-source charge
gate-to-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
internal drain inductance
VGS = 5 V; VDD = 44 V;
ID = 25 A; Figure 14
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 12
VDD = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 10 Ω
from drain lead 6 mm from
package to centre of die
from contact screw on
mounting base to centre of
die SOT78
from upper edge of drain
mounting base to centre of
die SOT404
Ls internal source inductance from source lead to source
bond pad
9397 750 10277
Product data
Rev. 02 — 8 October 2002
Min
55
50
1.1
0.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ Max Unit
--V
--V
1.5 2
--
- 2.3
0.02 1
- 500
2 100
V
V
V
µA
µA
nA
3.5
-
-
3.1
95
17
37
7665
1044
466
63
232
273
178
4.5
3.5
4.2
8.4
4.4
3.7
-
-
-
10220
1253
638
-
-
-
-
-
-
mΩ
mΩ
mΩ
mΩ
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
nH
nH
2.5 -
nH
7.5 -
nH
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
5 of 15
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Philips Semiconductors
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BUK95/964R2-55B
TrenchMOS™ logic level FET
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)
SOT404
D1
D
HD
E
2
13
ee
b
A
A1
mounting
base
Lp
c
Q
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A A1 b
c
D
max.
D1
mm 4.50 1.40 0.85 0.64 11 1.60
4.10 1.27 0.60 0.46
1.20
E
10.30
9.70
e
2.54
Lp HD Q
2.90 15.80 2.60
2.10 14.80 2.20
OUTLINE
VERSION
SOT404
IEC
Fig 17. SOT404 (D2-PAK)
9397 750 10277
Product data
REFERENCES
JEDEC
EIAJ
Rev. 02 — 8 October 2002
EUROPEAN
PROJECTION
ISSUE DATE
99-06-25
01-02-12
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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