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AD9272 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9272은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 AD9272 기능
기능 Octal LNA/VGA/AAF/ADC and Crosspoint Switch
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AD9272 데이터시트, 핀배열, 회로
FEATURES
8 channels of LNA, VGA, AAF, and ADC
Low noise preamplifier (LNA)
Input-referred noise voltage = 0.75 nV/√Hz
(gain = 21.3 dB) @ 5 MHz typical
SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB
Single-ended input; VIN maximum = 733 mV p-p/
550 mV p-p/367 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW) > 100 MHz
Full-scale (FS) output = 4.4 V p-p differential
Variable gain amplifier (VGA)
Attenuator range = −42 dB to 0 dB
SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable 2nd-order low-pass filter (LPF) from
8 MHz to 18 MHz
Programmable high-pass filter (HPF)
Analog-to-digital converter (ADC)
12 bits at 10 MSPS to 80 MSPS
SNR = 70 dB
SFDR = 75 dB
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Data and frame clock outputs
Includes an 8 × 8 differential crosspoint switch to support
continuous wave (CW) Doppler
Low power, 195 mW per channel at 12 bits/40 MSPS (TGC)
120 mW per channel in CW Doppler
Flexible power-down modes
Overload recovery in <10 ns
Fast recovery from low power standby mode, <2 μs
100-lead TQFP
APPLICATIONS
Medical imaging/ultrasound
Automotive radar
GENERAL DESCRIPTION
The AD9272 is designed for low cost, low power, small size, and
ease of use. It contains eight channels of a low noise preamplifier
(LNA) with a variable gain amplifier (VGA), an antialiasing
filter (AAF), and a 12-bit, 10 MSPS to 80 MSPS analog-to-
digital converter (ADC).
Each channel features a variable gain range of 42 dB, a fully
differential signal path, an active input preamplifier termination, a
maximum gain of up to 52 dB, and an ADC with a conversion
rate of up to 80 MSPS. The channel is optimized for dynamic
performance and low power in applications where a small
package size is critical.
Octal LNA/VGA/AAF/ADC
and Crosspoint Switch
AD9272
FUNCTIONAL BLOCK DIAGRAM
LOSW-A
LO-A
LI-A
LG-A
LNA
VGA
LOSW-B
LO-B
LI-B
LG-B LNA VGA
LOSW-C
LO-C
LI-C
LG-C LNA VGA
LOSW-D
LO-D
LI-D
LG-D
LNA
VGA
LOSW-E
LO-E
LI-E
LG-E
LNA
VGA
LOSW-F
LO-F
LI-F
LG-F LNA VGA
LOSW-G
LO-G
LI-G
LG-G
LNA
VGA
LOSW-H
LO-H
LI-H
LG-H LNA VGA
SWITCH
ARRAY
AD9272
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTA+
DOUTA–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTB+
DOUTB–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTC+
DOUTC–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTD+
DOUTD–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTE+
DOUTE–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTF+
DOUTF–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTG+
DOUTG–
AAF
12-BIT
ADC
REFERENCE
SERIAL
LVDS
DOUTH+
DOUTH–
FCO+
FCO–
DCO+
DCO–
Figure 1.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. The LNA input-referred noise voltage is typically
0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred
noise voltage of the entire channel is 0.85 nV/√Hz at maximum
gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB
LNA gain, the input SNR is about 92 dB. In CW Doppler mode,
the LNA output drives a transconductance amp that is switched
through an 8 × 8 differential crosspoint switch. The switch is
programmable through the SPI.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.




AD9272 pdf, 반도체, 판매, 대치품
The AD9272 requires a LVPECL-/CMOS-/LVDS-compatible
sample rate clock for full performance operation. No external
reference or driver components are required for many
applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO±) for
capturing data on the output and a frame clock (FCO±) trigger
for signaling a new output byte are provided.
Powering down individual channels is supported to increase
battery life for portable applications. There is also a standby
mode option that allows quick power-up for power cycling. In
CW Doppler operation, the VGA, antialiasing filter (AAF), and
ADC are powered down. The power of the time gain control
(TGC) path scales with selectable speed grades.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as a programmable clock, data
alignment, and programmable digital test pattern generation. The
digital test patterns include built-in fixed patterns, built-in
pseudorandom patterns, and custom user-defined test patterns
entered via the serial port interface.
AD9272
Fabricated in an advanced CMOS process, the AD9272 is
available in a 16 mm × 16 mm, RoHS-compliant, 100-lead
TQFP. It is specified over the industrial temperature range of
−40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight channels are contained in a
small, space-saving package. A full TGC path, ADC, and
crosspoint switch are contained within a 100-lead, 16 mm ×
16 mm TQFP.
2. Low Power of 195 mW Per Channel at 40 MSPS.
3. Integrated Crosspoint Switch. This switch allows numerous
multichannel configuration options to enable the CW
Doppler mode.
4. Ease of Use. A data clock output (DCO±) operates up to
480 MHz and supports double data rate (DDR) operation.
5. User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.
6. Integrated Second-Order Antialiasing Filter. This filter is
placed between the VGA and the ADC and is programmable
from 8 MHz to 18 MHz.
Rev. C | Page 3 of 44

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AD9272 전자부품, 판매, 대치품
AD9272
AD9272-40
AD9272-65
AD9272-80
Parameter 1
Conditions
Min Typ
Max Min Typ
Max Min Typ
Max Unit
GAIN ACCURACY
25°C
Gain Law Confor- 0 V < GAIN+ <
1.5
1.5
1.5 dB
mance Error
0.16 V
0.16 V < GAIN+ <
1.44 V
−1.5
+1.5 −1.5
+1.5 −1.6
+1.6 dB
1.44 V < GAIN+ <
−2.5
−2.5
−2.5 dB
1.6 V
Linear Gain Error
GAIN+ = 0.8 V,
normalized for
ideal AAF loss
−1.5
+1.5 −1.5
+1.5 −1.6
+1.6 dB
Channel-to-Channel 0.16 V < GAIN+ <
0.1
0.1
0.1 dB
Matching
1.44 V
GAIN CONTROL
INTERFACE
Normal Operating
Range
0 1.6 0 1.6 0 1.6 V
Gain Range
GAIN+ = 0 V to
42
42
42 dB
1.6 V
Scale Factor
28.5 28.5 28.5 dB/V
Response Time
42 dB change
750
750
750 ns
Gain+ Impedance Single-ended
10
10
10 MΩ
Gain− Impedance Single-ended
70
70
70 kΩ
CW DOPPLER MODE
Transconductance
(differential)
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB
5.4/7.3/10.9
5.4/7.3/10.9
5.4/7.3/10.9
mA/V
Output Level Range CW Doppler
(differential)
output pins
1.5
3.6 1.5
3.6 1.5
3.6 V
Input-Referred
Noise Voltage
Input-Referred
Dynamic Range
Two-Tone IMD3
(2 × F1 − F2)
Distortion
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
RS = 0 Ω,
RFB = ∞,
RL = 675 Ω
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
RS = 0 Ω,
RFB = ∞
fIN1 = 5.0 MHz at
−1 dBFS (FS at LNA
input),
fIN2 = 5.01 MHz at
−21 dBFS (FS at
LNA input),
LNA gain = 21.3 dB
2.35/1.82/1.31
161/161/160
−70
2.35/1.82/1.31
161/161/160
−70
2.35/1.82/1.31
nV/√Hz
161/161/160
dBFS/√Hz
−70 dBc
Output DC Bias
Per channel
2.4
2.4
2.4 mA
(single-ended)
Maximum Output Per channel
±2
±2
±2 mA p-p
Swing (single-
ended)
POWER SUPPLY
AVDD1
1.7 1.8
1.9 1.7 1.8
1.9 1.7 1.8
1.9 V
AVDD2
2.7 3.0
3.6 2.7 3.0
3.6 2.7 3.0
3.6 V
DRVDD
1.7 1.8
1.9 1.7 1.8
1.9 1.7 1.8
1.9 V
Rev. C | Page 6 of 44

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