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PDF AD9277 Data sheet ( Hoja de datos )
| Número de pieza | AD9277 | |
| Descripción | Octal LNA/VGA/AAF/14-Bit ADC And CW I/Q Demodulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9277 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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www.DataSheet4U.com
Octal LNA/VGA/AAF/14-Bit ADC
and CW I/Q Demodulator
AD9277
FEATURES
8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator
Low noise preamplifier (LNA)
Input-referred noise: 0.75 nV/√Hz typical at 5 MHz
(gain = 21.3 dB)
SPI-programmable gain: 15.6 dB/17.9 dB/21.3 dB
Single-ended input: VIN maximum = 733 mV p-p/
550 mV p-p/367 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW) > 100 MHz
Full-scale (FS) output: 4.4 V p-p differential
Variable gain amplifier (VGA)
Attenuator range: −42 dB to 0 dB
Postamp gain: 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable second-order LPF from 8 MHz to 18 MHz
Programmable HPF
Analog-to-digital converter (ADC)
14 bits at 10 MSPS to 50 MSPS
SNR: 73 dB
SFDR: 75 dB
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Data and frame clock outputs
CW mode I/Q demodulator
Individual programmable phase rotation
Output dynamic range per channel >160 dBFS/√Hz
Low power: 207 mW per channel at 14 bits/50 MSPS (TGC),
94 mW per channel for CW Doppler
Flexible power-down modes
Overload recovery in <10 ns
Fast recovery from low power standby mode: <2 μs
100-lead TQFP_EP
APPLICATIONS
Medical imaging/ultrasound
Automotive radar
PRODUCT HIGHLIGHTS
1. Small Footprint.
Eight channels are contained in a small, space-saving
package. Full TGC path, ADC, and I/Q demodulator
contained within a 100-lead, 16 mm × 16 mm TQFP.
2. Low Power.
In TGC mode, low power of 207 mW per channel
at 50 MSPS. In CW mode, ultralow power of 94 mW
per channel.
3. Integrated High Dynamic Range I/Q Demodulator with
Phase Rotation.
4. Ease of Use.
A data clock output (DCO±) operates up to 480 MHz
and supports double data rate (DDR) operation.
5. User Flexibility.
Serial port interface (SPI) control offers a wide range of
flexible features to meet specific system requirements.
6. Integrated Second-Order Antialiasing Filter.
This filter is placed before the ADC and is programmable
from 8 MHz to 18 MHz.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 PDWN STBY
DRVDD
LO-A TO LO-H
LOSW-A TO LOSW-H
LI-A TO LI-H
LG-A TO LG-H
LNA
I/Q
DEMODULATOR
VGA
AAF
8 CHANNELS
14-BIT
ADC
SERIAL
LVDS
DOUTA+ TO DOUTH+
DOUTA– TO DOUTH–
LO
GENERATION
REFERENCE
SERIAL
PORT
INTERFACE
DATA
RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
www.DataSheet4U.com
Parameter1
Noise Figure
Active Termination Matched
Unterminated
Correlated Noise Ratio
Output Offset
Signal-to-Noise Ratio (SNR)
Harmonic Distortion
Second Harmonic
Third Harmonic
Two-Tone Intermodulation (IMD3)
Channel-to-Channel Crosstalk
Channel-to-Channel Delay
Variation
PGA Gain
GAIN ACCURACY
Gain Law Conformance Error
Linear Gain Error
Channel-to-Channel Matching
GAIN CONTROL INTERFACE
Normal Operating Range
Gain Range
Scale Factor
Response Time
GAIN+ Impedance
GAIN− Impedance
CW DOPPLER MODE
LO Frequency
Phase Increment
Output DC Bias (Single-Ended)
Maximum Output Swing
Transconductance (Differential)
Input-Referred Noise Voltage
Test Conditions/Comments
GAIN+ = 1.6 V, RS = 50 Ω
LNA gain = 15.6 dB, RFB = 200 Ω
LNA gain = 17.9 dB, RFB = 250 Ω
LNA gain = 21.3 dB, RFB = 350 Ω
LNA gain = 15.6 dB, RFB = ∞
LNA gain = 17.9 dB, RFB = ∞
LNA gain = 21.3 dB, RFB = ∞
No signal, correlated/uncorrelated
fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V
fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V
fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V
fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V
fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V
fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V
fRF1 = 5.015 MHz, fRF2 = 5.020 MHz,
ARF1 = 0 dB, ARF2 = −20 dB, GAIN+ = 1.6 V,
IMD3 relative to ARF2
fIN = 5 MHz at −1 dBFS
Overrange condition2
Full TGC path, fIN = 5 MHz, GAIN+ = 0 V to 1.6 V
Differential input to differential output
25°C
0 < GAIN+ < 0.16 V
0.16 V < GAIN+ < 1.44 V
1.44 V < GAIN+ < 1.6 V
GAIN+ = 0.8 V, normalized for ideal AAF loss
0.16 V < GAIN+ < 1.44 V
GAIN+ = 0 V to 1.6 V
42 dB change
Single-ended
Single-ended
fLO = f4LO/4
Per channel
CWI+, CWI−, CWQ+, CWQ−
Per CWI+, CWI−, CWQ+, CWQ−, per channel
enabled
Demodulated IOUT/VIN, each I or Q output
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
RS = 0 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
Min
−110
−1.5
−1.5
0
−42
1
AD9277
Typ Max Unit
7.5 dB
6.2 dB
4.5 dB
4.6 dB
3.6 dB
2.8 dB
−30 dB
+110
LSB
67.5 dBFS
59 dBFS
−65 dBc
−70 dBc
−72 dBc
−60 dBc
−55 dBc
−70
−65
0.3
21/24/27/30
1.5
−2.5
0.1
28.5
750
10
70
22.5
1.5
+1.5
+1.5
1.6
0
10
±1.25
dB
dB
Degrees
dB
dB
dB
dB
dB
dB
V
dB
dB/V
ns
MΩ
kΩ
MHz
Degrees
V
mA
1.8 mA/V
2.4 mA/V
3.5 mA/V
1.5 nV/√Hz
1.4 nV/√Hz
1.3 nV/√Hz
Rev. 0 | Page 5 of 48
5 Page 
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9277
LI-E 1
LG-E 2
AVDD2 3
AVDD1 4
LO-F 5
LOSW-F 6
LI-F 7
LG-F 8
AVDD2 9
AVDD1 10
LO-G 11
LOSW-G 12
LI-G 13
LG-G 14
AVDD2 15
AVDD1 16
LO-H 17
LOSW-H 18
LI-H 19
LG-H 20
AVDD2 21
AVDD1 22
CLK– 23
CLK+ 24
AVDD1 25
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9277
TOP VIEW
(Not to Scale)
75 LI-D
74 LG-D
73 AVDD2
72 AVDD1
71 LO-C
70 LOSW-C
69 LI-C
68 LG-C
67 AVDD2
66 AVDD1
65 LO-B
64 LOSW-B
63 LI-B
62 LG-B
61 AVDD2
60 AVDD1
59 LO-A
58 LOSW-A
57 LI-A
56 LG-A
55 AVDD2
54 AVDD1
53 CSB
52 SDIO
51 SCLK
NOTES
1. THE EXPOSED PAD SHOULD BE TIED TO A QUIET ANALOG GROUND.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Name
0, 96, 97, 98
GND
1 LI-E
2 LG-E
3, 9, 15, 21, 55, 61,
67, 73, 85, 86, 91
AVDD2
4, 10, 16, 22, 25, 50, AVDD1
54, 60, 66, 72
5 LO-F
6 LOSW-F
7 LI-F
8 LG-F
11 LO-G
12 LOSW-G
13 LI-G
14 LG-G
17 LO-H
18 LOSW-H
19 LI-H
20 LG-H
Description
Ground. Exposed paddle should be tied to a quiet analog ground.
LNA Analog Input for Channel E.
LNA Ground for Channel E.
3.0 V Analog Supply.
1.8 V Analog Supply.
LNA Analog Inverted Output for Channel F.
LNA Analog Switched Output for Channel F.
LNA Analog Input for Channel F.
LNA Ground for Channel F.
LNA Analog Inverted Output for Channel G.
LNA Analog Switched Output for Channel G.
LNA Analog Input for Channel G.
LNA Ground for Channel G.
LNA Analog Inverted Output for Channel H.
LNA Analog Switched Output for Channel H.
LNA Analog Input for Channel H.
LNA Ground for Channel H.
Rev. 0 | Page 11 of 48
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9277.PDF ] | |
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