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Número de pieza | DS90UR124Q | |
Descripción | (DS90UR124Q / DS90UR241Q) 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset | |
Fabricantes | National Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de DS90UR124Q (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
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DS90UR241Q
DS90UR124Q
September 4, 2009
5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and
Deserializer Chipset
General Description
The DS90UR241/124 Chipset translates a 24-bit parallel bus
into a fully transparent data/control FPD-Link II LVDS serial
stream with embedded clock information. This chipset is ide-
ally suited for driving graphical data to displays requiring 18-
bit color depth - RGB666 + HS, VS, DE + 3 additional general
purpose data channels. This single serial stream simplifies
transferring a 24-bit bus over PCB traces and cable by elim-
inating the skew problems between parallel data and clock
paths. It saves system cost by narrowing data paths that in
turn reduce PCB layers, cable width, and connector size and
pins.
The DS90UR241/124 incorporates FPD-Link II LVDS signal-
ing on the high-speed I/O. FPD-Link II LVDS provides a low
power and low noise environment for reliably transferring data
over a serial transmission path. By optimizing the Serializer
output edge rate for the operating frequency range EMI is fur-
ther reduced.
In addition, the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects. Using National Semiconductor’s proprietary
random lock, the Serializer’s parallel data are randomized to
the Deserializer without the need of REFCLK.
Features
■ Supports displays with 18-bit color depth
■ 5MHz to 43MHz pixel clock
■ Automotive grade product AEC-Q100 grade 2 qualified
■ 24:1 interface compression
■ Embedded clock with DC Balancing supports AC-coupled
data transmission
■ Capable to drive up to 10 meters shielded twisted-pair
cable
■ No reference clock required (deserializer)
■ Meets ISO 10605 ESD - Greater than 8 kV HBM ESD
structure
■ Hot plug support
■ EMI Reduction - Serializer accepts spread spectrum input;
data randomization and shuffling on serial link;
Deserializer provides Adjustable PTO (progressive turn-
on) LVCMOS outputs
■ @Speed BIST (built-in self test) to validate LVDS
transmission path
■ Individual power-down controls for both Transmitter and
Receiver
■ Power supply range 3.3V ± 10%
■ 48-pin TQFP package for Transmitter and 64-pin TQFP
package for Receiver
■ Temperature range -40°C to +105°C
■ Backward compatible mode with DS90C241/DS90C124
Applications
■ Automotive Central Information Display
■ Automotive Instrument Cluster Display
■ Automotive Heads-Up Display
■ Remote Camera-based Driver Assistance Systems
Applications Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation 201945
20194527
www.national.com
1 page Serializer Input Timing Requirements for TCLK
wwOwv.eDrarteacSohmemete4Und.ceodmoperating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
tTCP
tTCIH
tTCIL
tCLKT
tJIT
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
(Figure 5)
Figure 4, ((Note 9))
(Note 10)
23.25
0.3T
0.3T
Typ
T
0.5T
0.5T
2.5
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
tLLHT
tLHLT
tDIS
tDIH
tHZD
tLZD
tZHD
tZLD
tPLD
tSD
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
DIN (0:23) Setup to TCLK
DIN (0:23) Hold from TCLK
DOUT ± HIGH to TRI-STATE Delay
DOUT ± LOW to TRI-STATE Delay
DOUT ± TRI-STATE to HIGH Delay
DOUT ± TRI-STATE to LOW Delay
Serializer PLL Lock Time
Serializer Delay
RL = 100Ω, VODSEL = L,
CL = 10 pF to GND, (Figure 3)
RL = 100Ω, CL = 10 pF to GND,
(Note 9), (Figure 5)
RL = 100Ω,
CL = 10 pF to GND,
(Note 6), (Figure 6)
RL = 100Ω
RL = 100Ω, PRE = OFF,
RAOFF = L, TRFB = H,
(Figure 8)
4
4
3.5T+2
RL = 100Ω, PRE = OFF,
RAOFF = L, TRFB = L,
(Figure 8)
3.5T+2
TxOUT_E_O TxOUT_Eye_Opening.
TxOUT_E_O centered on (tBIT/)2
5 MHz–43 MHz,
RL = 100Ω, CL = 10 pF to GND,
RANDOM pattern
(Note 10, Note 11), (Note 14)
(Figure 9)
0.76
Typ
245
264
10
10
75
75
0.84
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
tRCP
Receiver out Clock Period
tRCP = tTCP,
PTOSEL = H
RCLK
(Figure 15)
23.25
tRDC RCLK Duty Cycle
PTOSEL = H,
SLEW = L
45
tCLH
LVCMOS Low-to-High
CL = 4 pF
ROUT [0:23],
Transition Time
(lumped load), RCLK, LOCK
tCHL
LVCMOS High-to-Low
SLEW = H
Transition Time
(Note 9)
tCLH
LVCMOS Low-to-High
CL = 4 pF
ROUT [0:23],
Transition Time
(lumped load), RCLK, LOCK
tCHL
LVCMOS High-to-Low
SLEW = L
Transition Time
(Note 9)
Typ
T
50
1.5
1.5
2.0
2.0
Max
200
0.7T
0.7T
±100
Units
ns
ns
ns
ns
ps
Max
550
550
15
15
150
150
10
Units
ps
ps
ns
ns
ns
ns
ns
ns
ms
3.5T+10
ns
3.5T+10
ns
UI
Max Units
200 ns
55 %
2.5 ns
2.5 ns
3.5 ns
3.5 ns
5 www.national.com
5 Page www.DataSheet4U.com
20194513
FIGURE 13. Deserializer TRI-STATE Test Circuit and Timing
FIGURE 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
20194514
11 www.national.com
11 Page |
Páginas | Total 26 Páginas | |
PDF Descargar | [ Datasheet DS90UR124Q.PDF ] |
Número de pieza | Descripción | Fabricantes |
DS90UR124 | (DS90UR124 / DS90UR241) DC-Balanced 24-Bit LVDS Serializer and Deserializer | National Semiconductor |
DS90UR124-Q1 | DS90URxxx-Q1 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset (Rev. O) | Texas Instruments |
DS90UR124Q | (DS90UR124Q / DS90UR241Q) 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset | National Semiconductor |
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