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49LF004B PDF 데이터시트 ( Data , Function )

부품번호 49LF004B 기능
기능 SST49LF004B
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49LF004B 데이터시트, 핀배열, 회로
4 Mbit LPC Firmware Flash
SST49LF004B
FEATURES:
SST49LF004B4Mb LPC Firmware memory
Data Sheet
• SST49LF004B: 512K x8 (4 Mbit)
• Conforms to Intel LPC Interface Specification 1.1
– Supports Single-Byte LPC Memory and
Firmware Memory Cycle Types
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 64 KByte overlay blocks
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
• Two Operational Modes
– Low Pin Count (LPC) interface mode for
in-system operation
– Parallel Programming (PP) mode for fast
production programming
• LPC Interface Mode
– 5-signal LPC bus interface supporting byte Read
and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write
protect for entire chip and/or top Boot Block
– Block Locking Registers for individual block
write-lock and lock-down protection
– JEDEC Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write
detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and 8-pin data
I/O interface
– Supports fast programming in-system on
programmer equipment
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 40-lead TSOP (10mm x 20mm)
www.DaPtaRShOeeDt4UU.CcoTm DESCRIPTION
The SST49LF004B flash memory device is designed to
interface with host controllers (chipsets) that support a low-
pin-count (LPC) interface for BIOS applications. The
SST49LF004B device complies with Intel’s LPC Interface
Specification 1.1, supporting single-byte Firmware Memory
and LPC Memory cycle types.
The SST49LF004B is backward compatible to the
SST49LF00xA Firmware Hub and the SST49LF0x0A LPC
Flash. In this document, FWH mode in the SST49LF00xA
specification is referenced as the Firmware Memory Read/
Write cycle and LPC mode in the SST49LF0x0A specifica-
tion is referenced as the LPC Memory Read/Write cycle.
Two interface modes are supported by the SST49LF004B:
LPC mode (Firmware Memory and LPC Memory cycle
types) for in-system operations and Parallel Programming
(PP) mode to interface with programming equipment.
The SST49LF004B flash memory device is manufactured
with SST’s proprietary, high-performance SuperFlash tech-
nology. The split-gate cell design and thick-oxide tunneling
injector attain greater reliability and manufacturability com-
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
1
pared with alternative approaches. The SST49LF004B
device significantly improves performance and reliability,
while lowering power consumption. The SST49LF004B
device writes (Program or Erase) with a single 3.0-3.6V
power supply.
The SST49LF004B provides a maximum Byte-Program
time of 20 µsec. The entire memory can be erased and
programmed byte-by-byte in 8 seconds when using status
detection features such as Toggle Bit or Data# Polling to
indicate the completion of Program operation. To protect
against inadvertent writes, the SST49LF004B device has
on-chip hardware and software write protection schemes. It
is offered with a typical endurance of 100,000 cycles. Data
retention is rated at greater than 100 years.
The SST49LF004B uses less energy during Erase and
Program than alternative flash memory technologies. The
total energy consumed is a function of the applied voltage,
current and time of application. Since for any given voltage
range the SuperFlash technology uses less current to pro-
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Intel is a registered trademark of Intel Corporation.
These specifications are subject to change without notice.




49LF004B pdf, 반도체, 판매, 대치품
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
LIST OF FIGURES
FIGURE 1: Pin Assignments for 32-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FIGURE 2: Pin Assignments for 40-lead TSOP (10mm x 20mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FIGURE 3: Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
FIGURE 4: Firmware Memory Read Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
FIGURE 5: Firmware Memory Write Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
FIGURE 6: LPC Memory Read Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
FIGURE 7: LPC Memory Write Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
FIGURE 8: LCLK Waveform (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FIGURE 9: Output Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FIGURE 10: Input Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FIGURE 11: Reset Timing Diagram (LPC Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FIGURE 12: Reset Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FIGURE 13: Read Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FIGURE 14: Write Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FIGURE 15: Data# Polling Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FIGURE 16: Toggle Bit Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FIGURE 17: Byte-Program Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FIGURE 18: Sector-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FIGURE 19: Block-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FIGURE 20: Chip-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FIGURE 21: Software ID Entry and Read (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIGURE 22: Software ID Exit (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIGURE 23: AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FIGURE 24: A Test Load Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
www.DataSheet4U.com
©2003 Silicon Storage Technology, Inc.
4
S71232-02-000
12/03

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49LF004B 전자부품, 판매, 대치품
4 Mbit LPC Firmware Flash
SST49LF004B
PIN ASSIGNMENTS
Data Sheet
A7(GPI1)
A6 (GPI0)
A5 (WP#)
A4 (TBL#)
A3 (ID3)
A2 (ID2)
A1 (ID1)
A0 (ID0)
DQ0 (LAD0)
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
32-lead PLCC
9 25
10
Top View
24
11 23
12 22
13 21
14 15 16 17 18 19 20
MODE (MODE)
VSS (VSS)
NC
NC
VDD (VDD)
OE# (INIT#)
WE# (LFRAME#)
NC
DQ7 (RES)
( ) Designates LPC Mode
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC
1232 32-plcc P1.0
www.DataSheet4U.com
NC (NC)
MODE (MODE)
NC (NC)
NC (NC)
NC (NC)
NC (NC)
A10 (GPI4)
NC (NC)
R/C# (LCLK)
VDD
NC (NC)
RST# (RST#)
NC (NC)
NC (NC)
A9 (GPI3)
A8 (GPI2)
A7 (GPI1)
A6 (GPI0)
A5 (WP#)
A4 (TBL#)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Standard Pinout
Top View
Die Up
40 VSS
39 VDD
38 (LFRAME#) WE#
37 (INIT#) OE#
36 (NC) NC
35 (RES) DQ7
34 (RES) DQ6
33 (RES) DQ5
32 (RES) DQ4
31 (NC) NC
30 VSS
29 VSS
28 (LAD3) DQ3
27 (LAD2) DQ2
26 (LAD1) DQ1
25 (LAD0) DQ0
24 (ID0) A0
23 (ID1) A1
22 (ID2) A2
21 (ID3) A3
1232 40-tsop P2.0
( ) Designates LPC Mode
FIGURE 2: PIN ASSIGNMENTS FOR 40-LEAD TSOP (10MM X 20MM)
©2003 Silicon Storage Technology, Inc.
7
S71232-02-000
12/03

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관련 데이터시트

부품번호상세설명 및 기능제조사
49LF004

A49LF004

AMIC
AMIC
49LF004A

SST49LF004A

Silicon Storage Technology
Silicon Storage Technology

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