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WV3EG128M72EFSR-D3 데이터시트 PDF




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기능 1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL
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WV3EG128M72EFSR-D3 데이터시트, 핀배열, 회로
White Electronic Designs WV3EG128M72EFSR-D3
ADVANCED*
1GB – 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA
FEATURES
Double-data-rate architecture
DDR266 and DDR333
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power Supply:
• VCC = VCCQ = +2.5V ±0.2V (100, 133 and
166MHz)
184 pin DIMM package
PCB height:
• D3: 29.97mm (1.18")
NOTE: Consult factory for availability of:
• Lead-Free Products
• Vendor source control options
www.DatIandSuhsteriaeltt4emUp.ecroatmure options
DESCRIPTION
The WV3EG128M72EFSR is a 128Mx72 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM component. The module consists of eighteen
64Mx8 DDR components in FBGA packages mounted on
a 184 Pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lenths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
March 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




WV3EG128M72EFSR-D3 pdf, 반도체, 판매, 대치품
White Electronic Designs WV3EG128M72EFSR-D3
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Symbol
VIN, VOUT
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Current
VCC, VCCQ
TSTG
PD
IOS
Note:
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
Value
-0.5 to 3.6
-1.0 to 3.6
-55 to +150
18
50
Units
V
V
°C
W
mA
DC CHARACTERISTICS
0°C TA 70°C, VCC = 2.5V ± 0.2V
Parameter
Supply Voltage (for device with nominal VCC of 2.5V)
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (systems)
Input Logic High Voltage
Input Logic Low Voltage
Input Voltage Level, CK and CK# inputs
Input Differential Voltage, CK and CK# inputs
Input Crossing Point Voltage, CK and CK# inputs
Input Leakage Current
Output Leakage Current
Output High Current (Normal strength driver); VOUT = VTT + 0.84V
Output High Current (Normal strength driver); VOUT = VTT - 0.84V
Output High Current (Half strength driver); VOUT = VTT + 0.45V
Output High Current (Half strength driver); VOUT = VTT - 0.45V
Symbol
VCC
VCCQ
VREF
VTT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
IL
IOZ
IOH
IOL
IOH
IOL
Min
2.3
2.3
VCCQ/2-50mV
VREF -0.04
VREF +0.15
-0.3
-0.3
0.3
1.15
-2
-5
-16.8
16.8
-9
9
Max
2.3
2.3
VCCQ/2+50mV
VREF +0.04
VCCQ +0.3
VREF -0.15
VCCQ +0.3
VCCQ +0.6
1.35
2
5
Unit
V
V
V
V
V
V
V
V
V
uA
uA
mA
mA
mA
mA
Notes:
1w. wIwnc.lDudaetsa±S2h5meeVtm4aUrg.icnofomr DC offset on VREF, and a combined total of ± 50mV
4. These parameters should be tested at the pin on actual components and may
margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The
be checked at either the pin or the pad in simulation. The AC and DC input
DRAM must accommodate DRAM current spikes on VREF and internal DRAM
specifications are relative to a VREF envelop that has been bandwidth limited to
noise coupled TO VREF, both of which may result in VREF noise. VREF should be
200MHZ.
de-coupled with an inductance of ≤ 3nH.
5. The value of VIX is expected to equal 0.5*VCCQ of the transmitting device and must
2. VTT is not applied directly to the device. VTT is a system supply for signal
track variations in the dc level of the same.
termination resistors, is expected to be set equal to VREF, and must track variations
6. These charactericteristics obey the SSTL-2 class II standards.
in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input
level on CK#.
CAPACITANCE
TA = 25°C. f = 1MHz, VCC = 2.5V
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#, CAS#, WE#)
Input Capacitance (CKE0, CKE1)
Input Capacitance (CK0#, CK0)
Input Capacitance (CS0#, CS1#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
Data input/output capacitance (CB0-CB7)
Symbol Max Unit
CIN1 11 pF
CIN2 11 pF
CIN3 11 pF
CIN4 12 pF
CIN5 11 pF
CIN6 15 pF
CIN7 11 pF
COUT 15 pF
COUT 15 pF
March 2005
Rev. 0
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

4페이지










WV3EG128M72EFSR-D3 전자부품, 판매, 대치품
White Electronic Designs WV3EG128M72EFSR-D3
ADVANCED
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
4. Timing Patterns :
• DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
• DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
www.DataRSehaedet4: UA.0coNmN R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
• DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
• DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
March 2005
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

7페이지


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WV3EG128M72EFSR-D3

1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL

White Electronic Designs
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