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WV3EG64M72ETSU-D3 데이터시트 PDF




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부품번호 WV3EG64M72ETSU-D3 기능
기능 512MB - 64Mx72 DDR SDRAM UNBUFFERED
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WV3EG64M72ETSU-D3 데이터시트, 핀배열, 회로
White Electronic Designs
WV3EG64M72ETSU-D3
PRELIMINARY*
512MB – 64Mx72 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
PC2700 @ CL 2.5
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power supply:
• VCC = VCCQ = +2.5V ±0.2V
184 pin DIMM package
• D3 PCB height: 28.58mm (1.125")
DESCRIPTION
The WV3EG64M72ETSU is a 64Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of nine 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
www.DataSheet4U.com
OPERATING FREQUENCIES
Clock Speed
CL-tRCD-tRP
DDR333 @CL=2.5
166MHz
2.5-3-3
October 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




WV3EG64M72ETSU-D3 pdf, 반도체, 판매, 대치품
White Electronic Designs
WV3EG64M72ETSU-D3
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Symbol
VIN, VOUT
Voltage on VCC supply relative to VSS
Voltage on VCCQ supply relative to VSS
Storage Temperature
Operating Temperature
Power Dissipation
Short Circuit Current
VCC
VCCQ
TSTG
TA
PD
IOS
Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
Value
-0.5 to 3.6
-1.0 to 3.6
-1.0 to 3.6
-55 to +150
0 to +70
9
50
Units
V
V
V
°C
°C
W
mA
DC CHARACTERISTICS
0°C TA 70°C, VCC = VCCQ = 2.5V ± 0.2V
Parameter
Supply voltage DDR266/DDR333 (nominal VCC of 2.5V)
I/O Supply voltage DDR266/DDR333 (nominal VCC of 2.5V)
I/O Reference voltage
I/O Termination voltage
Input logic high voltage
Input logic low voltage
Input voltage level, CK and CK#
Input differential voltage, CK and CK#
Input crossing point voltage, CK and CK#
Addr, CAS#,
RAS#, WE#
Input leakage current
CS#, CKE
CK, CK#
DM
wOutwput lweaka.geDcurraent t a S h e e t 4 U . c o m
Output high current (normal strengh); VOUT = V +0.84V
Output high current (normal strengh); VOUT = VTT -0.84V
Output high current (half strengh); VOUT = VTT +0.45V
Output high current (half strengh); VOUT = VTT -0.45V
Symbol
VCC
VCCQ
VREF
VTT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
II
IOZ
IOH
IOL
IOH
IOL
Min
2.3
2.3
0.49*VCCQ
VREF-0.04
VREF+0.15
-0.3
-0.3
0.36
0.3
-18
Max
2.7
2.7
0.51*VCCQ
VREF+0.04
VCCQ+0.30
VREF-0.15
VCCQ+0.30
VCCQ+0.60
VCCQ+0.60
18
-18 18
-6 6
-2 2
-5 5
-16.8 —
16.8 —
-9 —
9—
Unit
V
V
V
V
V
V
V
V
uA
uA
uA
uA
uA
mA
mA
mA
mA
Note
1
2
3
NOTES:
1. VREF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed ±2% of the DC
value
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = VCCQ = 2.5V
Parameter
Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#)
Input Capacitance (CKE0)
Input Capacitance (CS0#)
Input Capacitance (CK0 to CK2, CK0# to CK2#)
Input Capacitance (DM0-DM7)
Data and DQS input/output capacitance (DQ0-DQ63)
Symbol
Min
Max
Unit
CIN1 22 31 pF
CIN2 22 31 pF
CIN3 22 31 pF
CIN4 10 13 pF
CIN5 8
9 pF
COUT1
8
9 pF
Octobert 2005
Rev. 0
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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WV3EG64M72ETSU-D3 전자부품, 판매, 대치품
White Electronic Designs
WV3EG64M72ETSU-D3
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
Parameter
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge command
Autoprecharge write recovery + Precharge time
Note: These specifications apply to modules built with Samsung components only.
Symbol
tMRD
tDS
tDH
tIPW
tDIPW
tXSNR
tXSRD
tREFI
tQH
tHP
tQHS
tWPST
tRAP
tRAL
335
Min
12
0.45
0.45
2.2
1.75
75
200
tHP-tQHS
tCLmin or tCHmin
0.4
18
(tWR/tCK) +
(tRP/tCK)
Max
7.8
0.55
0.6
Unit
ns
ns
ns
ns
ns
ns
tCK
us
ns
ns
ns
ns
tCK
AC OPERATING TEST CONDITIONS
VCC = 2.5V, VCCQ = 2.5V, 0°C TA 70°C
Parameter/Condition
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
wwInwpu.Dt DaitffaeSrehnetiaeltV4oUlta.cgoe,mCK and CK# inputs
Input Crossing Point Voltage, CK and CK# inputs
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
VREF +0.31
0.7
0.5*VCCQ-0.2
Max
VREF -0.31
VCCQ+0.6
0.5*VCCQ+0.2
NOTES:
1. VIH overshoot: VIH = VCCQ +1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
VIL undershoot: VIL = -1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
Unit
V
V
V
V
Note
1
1
October 2005
Rev. 0
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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WV3EG64M72ETSU-D3

512MB - 64Mx72 DDR SDRAM UNBUFFERED

White Electronic Designs
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