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WV3HG128M72EER-D7 데이터시트 PDF




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부품번호 WV3HG128M72EER-D7 기능
기능 1GB - 128Mx72 DDR2 SDRAM REGISTERED
제조업체 White Electronic Designs
로고 White Electronic Designs 로고


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WV3HG128M72EER-D7 데이터시트, 핀배열, 회로
White Electronic Designs WV3HG128M72EER-D7
ADVANCED*
1GB – 128Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM
FEATURES
244-pin, dual in-line memory module (Mini-DIMM)
Fast data transfer rates: PC2-6400*, PCS-5300*,
PC2-4200 and PC2-3200
Utilizes 800*, 667*, 533 and 400 Mb/s DDR2
SDRAM components
VCC = VCCQ = 1.8V ±0.1V
VCCSPD = 1.7V to 3.6V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL): 3, 4, 5* and 6*
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
JEDEC Standard 1.8V I/O (SSTL_18 Compatible)
Gold (Au) edge contacts
Sinlge Rank
RoHS compliant
Package option
• 244 Pin Mini-DIMM
• PCB – 30.00mm (1.181") TYP
DESCRIPTION
The WV3HG128M72EER is a 128Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of nine 128Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
244-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
www.DataSheet4U.com
Clock Speed
CL-tRCD-tRP
*Consult factory for availability.
OPERATING FREQUENCIES
PC2-3200
200MHz
3-3-3
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
May 2006
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




WV3HG128M72EER-D7 pdf, 반도체, 판매, 대치품
White Electronic Designs WV3HG128M72EER-D7
ADVANCED
Symbol
VCC
VIN, VOUT
TSTG
IL
IOZ
IVREF
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V,VIN,0.95V; Other pins not under test = 0V
Output leakage current; 0V<VIN<VCC; DQs and ODT are disable
VREF leakage current; VREF = Valid VREF level
Command/Address,
RAS#, CAS#, WE#,
CK, CK#
DM
DQ, DQS, DQS#
Min
-0.5
-0.5
-55
-5
-10
-5
-5
-18
Max Units
2.3 V
2.3 V
100 °C
5 µA
10 µA
5 µA
5 µA
18 µA
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol Min Typical Max
Unit Notes
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
VCC
VREF
VTT
VCCSPD
1.7
0.49 x VCC
VREF-0.04
1.7
1.8
0.50 x VCC
VREF
-
1.9
0.51 x VCC
VREF+0.04
3.6
V
V
V
V
3
1
2
Notes:
1 VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. VCCQ of all IC's are tied to VCC.
www.DataSheet4U.com
INPUT/OUTPUT CAPACITANCE
TA=25 0 C, f=1 00MHz
Parameter
Input capacitance (A0 - A13, BA0 - BA1 ,RAS#,CAS#,WE#)
Input capacitance ( CKE0), (ODT0)
Input capacitance (CS0#)
Input capacitance (CK0, CK0#)
Input capacitance (DM0 - DM8), (DQS0 - DQS8)
Input capacitance (DQ0 - DQ63), (CB0 - CB7)
Symbol
Min
Max
Unit
CIN1 11 12 pF
CIN2 11 12 pF
CIN3 11 12 pF
CIN4 10 11 pF
CIN5 (665)
6.5
8
pF
CIN5 (534,403)
6.5
7.5
pF
COUT1 (665)
6.5
8
pF
COUT1 (534,403)
6.5
7.5
pF
May 2006
Rev. 0
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

4페이지










WV3HG128M72EER-D7 전자부품, 판매, 대치품
White Electronic Designs WV3HG128M72EER-D7
ADVANCED
AC TIMING PARAMETERS
VCC = +1.8V ± 0.1V
Parameter
Symbol
806
Min Max
665
Min Max
534
Min Max
403
Min Max
Unit
Clock cycle time
CK high-level width
CK low-level width
CL=6
CL=5
CL=4
CL=3
Half clock period
Clock jitter
DQ output access time from CK/CK#
Data-out high impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Data hold skew factor
DQ-DQS hold, DQS to first DQ to go nonvalid, per
access
tCK(6) TBD TBD
tCK(5) TBD TBD 3000 8000 - - - - ps
tCK(4) TBD TBD 3750 8000 3,750 8,000 5,000 8,000 ps
tCK(3) TBD TBD 5000 8000 5,000 8,000 5,000 8,000 ps
tCH TBD TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tCL TBD TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tHP
MIN(tCH,
TBD TBD tCL)
MIN (tCH,
tCL)
MIN (tCH,
tCL)
ps
tJIT
TBD TBD -125 125 -125 125 -125 125
ps
tAC TBD TBD -450 +450 -500 +500 -600 +600 ps
tHZ TBD TBD
tAC(MAX)
tAC(MAX)
tAC(MAX) ps
tLZ
TBD
TBD tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX)
ps
tDS TBD TBD 100 100 150
tDH TBD TBD 175 225 275
tDIPW
TBD TBD 0.35
0.35
0.35
tCK
tQHS
TBD TBD
340
400
450 ps
tQH TBD TBD tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
Data valid output window (DVW)
www.DDQatSaiSnphuetehtig4hUp.culosemwidth
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
DQS-DQ skew, DOS to last DQ valid, per group, per
access
tDVW
tQH
TBD TBD - tDQSQ
tQH
- tDQSQ
tQH
- tDQSQ
ns
tDQSH
TBD TBD 0.35
0.35
0.35
tCK
tDQSL
TBD TBD 0.35
0.35
0.35
tCK
tDQSCK TBD TBD -400 +400 -450 +450 -500 +500 ps
tDSS TBD TBD 0.2 0.2 0.2
tCK
tDSH TBD TBD 0.2 0.2 0.2
tCK
tDQSQ TBD TBD 240 300 350 ps
DQS read preamble
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
Write command to first DQS latching transition
tRPRE
TBD TBD 0.9 1.1 0.9 1.1 0.9 1.1
tCK
tRPST
TBD TBD 0.4 0.6 0.4 0.6 0.4 0.6
tCK
tWPRES TBD TBD
0
0
0
ps
tWPRE TBD TBD 0.35 0.35 0.35
tCK
tWPST
TBD TBD 0.4 0.6 0.4 0.6 0.4 0.6
tCK
tDQSS TBD TBD WL-0.25 WL+0.25 WL-0.25 WL+0.25 WL-0.25 WL+0.25 tCK
AC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
May 2006
Rev. 0
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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WV3HG128M72EER-D7

1GB - 128Mx72 DDR2 SDRAM REGISTERED

White Electronic Designs
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