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부품번호 | WV3HG264M64EEU-D6 기능 |
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기능 | 1GB - 2x64Mx64 DDR2 SDRAM UNBUFFERED | ||
제조업체 | White Electronic Designs | ||
로고 | |||
White Electronic Designs WV3HG264M64EEU-D6
ADVANCED*
1GB – 2x64Mx64 DDR2 SDRAM UNBUFFERED
FEATURES
240-pin, dual in-line memory module
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
Utilizes 800*, 667*, 533 and 400 MT/s DDR2
SDRAM components
VCC = VCCQ = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL): 3, 4, 5 and 6
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Gold edge contacts
Dual Rank
RoHS compliant
Package option
• 240 Pin DIMM
• PCB – 30.00mm (1.181") TYP
DESCRIPTION
The WV3HG264M64EEU is a 2x64Mx64 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of sixteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
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Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
December 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs WV3HG264M64EEU-D6
ADVANCED
DC OPERATING CONDITIONS
All Voltages Referenced to VSS
Rating
Parameter
Symbol
Min.
Type
Max.
Units
Notes
Supply Voltage
VCC 1.7 1.8 1.9
V
1
I/O Supply Voltage
VCCQ
1.7
1.8
1.9
V
4
VCCL Supply Voltage
VCCL 1.7 1.8 1.9
V
4
I/O Reference Voltage
VREF
0.49*VCCQ
0.50*VCCQ
0.51*VCCQ
V
2
I/O Termination Voltage
VTT VREF-0.04 VREF VREF+0.04
V
3
Notes:
1. VCC and VCCQ must track each other. VCCQ must be less than or equal to VCC.
2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/- percent of the DC
value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
4. VCCQ tracks with VCC; VCCL track with VCC.
ABSOLUTE MAXIMUM RATINGS
SSTL_1.8V
Symbol
Parameter
Min Max Unit
VCC Voltage on VCC pin relative to VSS
- 1.0 2.3
V
VCCQ
Voltage on VCCQ pin relative to VSS
- 0.5 2.3
V
VCCL Voltage on VCCL pin relative to VSS
- 0.5 2.3
V
VIN, VOUT
Voltage on any pin relative to VSS
- 0.5 2.3
V
TSTG Storage Temperature
-55 100 °C
TCASE
Device operating Temperature
0 85 °C
www.DataILSheet4U.coInmput leakage current; Any input 0V<VIN<VCC; Command/Address, RAS#,
-80
80
uA
VREF input 0V<VIN<<0.95; Other pins not
CAS#, WE#
under test = 0V
CS#, CKE
-40 40 uA
CK, CK#
-30 30 uA
DM -10 10 uA
IOZ
Output leakage current; 0V<VOUT<VCCQ; DQs
DQ, DQS, DQS#
-10
10
uA
and ODT are disable
IVREF
VREF leakage current; VREF = Valid VREF level
-32 32 uA
December 2005
Rev. 0
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
4페이지 White Electronic Designs WV3HG264M64EEU-D6
ADVANCED
AC TIMING PARAMETERS
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
806 665 534 403
PARAMETER
Clock cycle time
CK high-level width
CK low-level width
CL = 6
CL = 5
CL = 4
CL = 3
SYMBOL
tCK (6)
tCK (5)
tCK (4)
tCK (3)
tCH
tCL
MIN
TBD
TBD
TBD
TBD
TBD
TBD
Half clock period
tHP TBD
DQ output access time from CK/CK#
Data-out high-impedance window from
CK/CK#
Data-out low-impedance window from
CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
A DQ and DM input pulse width (for each
input)
Data hold skew factor
DQ…DQS hold, DQS to first DQ to go
nonvalid, per access
tAC
tHZ
tLZ
tDS
tDH
tDIPW
tQHS
tQH
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Data valid output window (DVW)
tDVW
TBD
DQS input high pulse width
DQS input low pulse width
DQS output access time from CK/CK#
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DQS falling edge to CK rising … setup time
DQS falling edge from CK rising … hold time
DQS…DQ skew, DQS to last DQ valid, per
group,
per access
DQS read preamble
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
Write command to first DQS latching
transition
Address and control input pulse width for
each input
tDQSH
tDQSL
tDQSCK
tDSS
tDSH
tDQSQ
tRPRE
tRPST
tWPRES
tWPRE
tWPST
tDQSS
tIPW
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MAX MIN MAX MIN MAX MIN MAX
TBD
TBD 3000 8000
TBD 3750 8000 3,750 8,000 5,000 8,000
TBD 5680 8000 5,000 8,000 5,000 8,000
TBD 0.45 0.55 0.45 0.55 0.45 0.55
TBD 0.45 0.55 0.45 0.55 0.45 0.55
MIN (tCH,
TBD tCL)
MIN (tCH,
tCL)
MIN (tCH,
tCL)
TBD -450 +450 -500 +500 -600 +600
UNIT
ps
ps
ps
ps
tCK
tCK
ps
ps
TBD
tAC (MAX)
tAC (MAX)
tAC (MAX) ps
TBD tAC (MIN) tAC (MAX) tAC (MIN) tAC (MAX) tAC (MIN) tAC (MAX) ps
TBD 100 100 150 ps
TBD 225 225 275 ps
TBD 0.35 0.35 0.35 tCK
TBD 340 400 450 ps
TBD tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
tQH
TBD - tDQSQ
tQH
- tDQSQ
tQH
- tDQSQ
ns
TBD 0.35 0.35 0.35 tCK
TBD 0.35 0.35 0.35 tCK
TBD -400 +400 -450 +450 -500 +500 ps
TBD 0.2 0.2 0.2 tCK
TBD 0.2 0.2 0.2 tCK
TBD 240 300 350 ps
TBD 0.9 1.1 0.9 1.1 0.9 1.1 tCK
TBD 0.4 0.6 0.4 0.6 0.4 0.6 tCK
TBD 0 0 0 ps
TBD 0.35 0.35 0.35 tCK
TBD 0.4 0.6 0.4 0.6 0.4 0.6 tCK
TBD
WL WL + WL WL + WL WL +
- 0.25 0.25 - 0.25 0.25 - 0.25 0.25
tCK
TBD 0.6 0.6 0.6 tCK
NOTE:
• AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
December 2005
Rev. 0
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
7페이지 | |||
구 성 | 총 11 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
WV3HG264M64EEU-D4 | 1GB - 2x64Mx64 DDR2 SDRAM UNBUFFERED | White Electronic Designs |
WV3HG264M64EEU-D6 | 1GB - 2x64Mx64 DDR2 SDRAM UNBUFFERED | White Electronic Designs |
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