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부품번호 | WV3HG264M72EER-D7 기능 |
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기능 | 1GB - 2x64Mx72 DDR2 SDRAM REGISTERED | ||
제조업체 | White Electronic Designs | ||
로고 | |||
White Electronic Designs WV3HG264M72EER-D7
ADVANCED*
1GB – 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM
FEATURES
244-pin, dual in-line memory module (Mini-DIMM)
Fast data transfer rates: PC2-6400*, PCS-5300*,
PC2-4200 and PC2-3200
Utilizes 800, 667, 533 and 400 Mb/s DDR2 SDRAM
components
VCC = VCCQ = 1.8V ±0.1V
VCCSPD = 1.7V to 3.6V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL): 3, 4, 5 and 6
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
JEDEC Standard 1.8V I/O (SSTL_18 Compatible)
Gold (Au) edge contacts
Dual Rank
RoHS compliant
Package option
• 244 Pin Mini-DIMM
• PCB – 30.00mm (1.181") TYP
DESCRIPTION
The WV3HG264M72EER is a 2x64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
244-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
www.DataSheet4U.com
Clock Speed
CL-tRCD-tRP
*Consult factory for availability.
OPERATING FREQUENCIES
PC2-3200
200MHz
3-3-3
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
August 2006
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs WV3HG264M72EER-D7
ADVANCED
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Supply voltage
I/O Supply voltage
VCCL Supply voltage
I/O Reference voltage
I/O Termination voltage
Symbol
VCC
VCCQ
VCCL
VREF
VTT
Min
1 .7
1 .7
1 .7
0.49 x VCCQ
VREF-0.04
Typical
1 .8
1 .8
1 .8
0.50 x VCCQ
VREF
Max
1 .9
1 .9
1 .9
0.51 x VCCQ
VREF + 0.04
Unit
V
V
V
V
V
Notes
1
4
4
2
3
Notes:
1. VCC VCCQ must track each other. VCCQ must be less than or equal to VCC.
2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ±1 percent of the DC
value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
4. VCCQ tracks with VCC; VCCL track with VCC.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
MIN MAX Unit
VCC Voltage on VCC pin relative to VSS
-0.5 2.3
V
VCCQ
Voltage on VCCQ pin relative to VSS
-0.5 2.3
V
VCCL Voltage on VCCL pin relative to VSS
-0.5 2.3
V
VIN, VOUT Voltage on any pin relative to VSS
-0.5 2.3
V
TSTG Storage temperature
-55 100 °C
TCASE
Device operating temperature
0 85 °C
Command/Address,
RAS#, CAS#, WE#,
-5
5
µA
IL
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V<VIN<0.95V; Other pins not under test = 0V
CS#, CKE
CK, CK#
-10 10 µA
DM -10 10 µA
w
ww
IOZ
.
D
aOuttputaleaSkaghe cuerrenet; t 4 U . c o
0V<VOUT<VCCQ; DQs and ODT are disable
m
DQ, DQS, DQS#
-10
10
µA
IVREF VREF leakage current; VREF = Valid VREF level
-36 36 µA
INPUT/OUTPUT CAPACITANCE
TA=25 0 C, f=1 00MHz
Parameter
Input capacitance (A0 - A13, BA0 - BA1 ,RAS#,CAS#,WE#)
Input capacitance ( CKE0, CKE1), (ODT0, ODT1)
Input capacitance (CS0#, CS1#)
Input capacitance (CK0, CK0#)
Input capacitance (DM0 - DM8), (DQS0 - DQS8)
Input capacitance (DQ0 - DQ63), (CB0 - CB7)
Symbol
Min
Max
Unit
CIN1 9
11 pF
CIN2 9
11 pF
CIN3 9
11 pF
CIN4 10 11 pF
CIN5 (E6)
9
11 pF
CIN5 (E5)
9
12 pF
COUT1 (E6)
9
11 pF
COUT1 (E5)
9
12 pF
August 2006
Rev. 3
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
4페이지 White Electronic Designs WV3HG264M72EER-D7
ADVANCED
AC TIMING PARAMETERS
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Parameter
Symbol
806
Min Max
665
Min Max
534
Min Max
403
Min Max
Clock cycle time
CK high-level width
CK low-level width
CL=6
CL=5
CL=4
CL=3
Half clock period
Clock jitter
DQ output access time from CK/CK#
Data-out high impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Data hold skew factor
DQ-DQS hold, DQS to first DQ to go nonvalid, per
access
tCK(6) TBD TBD
tCK(5) TBD TBD 3000 8000 - - - -
tCK(4) TBD TBD 3750 8000 3,750 8,000 5,000 8,000
tCK(3) TBD TBD 5000 8000 5,000 8,000 5,000 8,000
tCH TBD TBD 0.45 0.55 0.45 0.55 0.45 0.55
tCL TBD TBD 0.45 0.55 0.45 0.55 0.45 0.55
tHP
MIN(tCH,
TBD TBD tCL)
MIN (tCH,
tCL)
MIN (tCH,
tCL)
tJIT TBD TBD -125 125 -125 125 -125 125
tAC TBD TBD -450 +450 -500 +500 -600 +600
tHZ TBD TBD
tAC(MAX)
tAC(MAX)
tAC(MAX)
tLZ TBD TBD tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX)
tDS TBD TBD 100 100 150
tDH TBD TBD 175 225 275
tDIPW
TBD TBD 0.35
0.35
0.35
tQHS
TBD TBD
340
400
450
tQH TBD TBD tHP - tQHS
tHP - tQHS
tHP - tQHS
Data valid output window (DVW)
www.DDQatSaiSnphuetehtig4hUp.culosemwidth
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
DQS-DQ skew, DOS to last DQ valid, per group, per
access
tDVW
tQH
TBD TBD - tDQSQ
tQH
- tDQSQ
tQH
- tDQSQ
tDQSH
TBD TBD 0.35
0.35
0.35
tDQSL
TBD TBD 0.35
0.35
0.35
tDQSCK TBD TBD -400 +400 -450 +450 -500 +500
tDSS TBD TBD 0.2 0.2 0.2
tDSH TBD TBD 0.2 0.2 0.2
tDQSQ TBD TBD 240 300 350
DQS read preamble
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
Write command to first DQS latching transition
tRPRE
TBD TBD 0.9 1.1 0.9 1.1 0.9 1.1
tRPST TBD TBD 0.4 0.6 0.4 0.6 0.4 0.6
tWPRES TBD TBD
0
0
0
tWPRE TBD TBD 0.35 0.35 0.35
tWPST TBD TBD 0.4 0.6 0.4 0.6 0.4 0.6
tDQSS TBD TBD WL-0.25 WL+0.25 WL-0.25 WL+0.25 WL-0.25 WL+0.25
AC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
Unit
ps
ps
ps
tCK
tCK
ps
ps
ps
ps
ps
tCK
ps
ps
ns
tCK
tCK
ps
tCK
tCK
ps
tCK
tCK
ps
tCK
tCK
tCK
August 2006
Rev. 3
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
WV3HG264M72EER-D7 | 1GB - 2x64Mx72 DDR2 SDRAM REGISTERED | White Electronic Designs |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |