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PDF MX25L12805D Data sheet ( Hoja de datos )
| Número de pieza | MX25L12805D | |
| Descripción | 128M-BIT [x 1] CMOS SERIAL FLASH | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX25L12805D
128M-BIT [x 1] CMOS SERIAL FLASH
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 134,217,728 x 1 bit structure
• 4096 equal sectors with 4K byte each
256 equal sectors with 64K byte each
- Any sector can be erased
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 50MHz serial clock (30pF + 1TTL Load)
- Fast program time: 1.4ms/page (typical, 256-byte per page) and 9us/byte (typical)
- Fast erase time: 60ms/sector (4KB per sector), 0.7s/block (64KB per block) and 80s/chip
- Acceleration mode:
- Chip erase time: 50s (typical)
• Low Power Consumption
- Low active read current: 25mA (max.) at 50MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 20uA (max.)
- Deep power-down mode 20uA (max.)
• Typical 100,000 erase/program cycle
• 10 years data retention
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SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions
- Additional 512-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte Device ID
- RES command, 1-byte Device ID
- REMS command, ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first
P/N: PM1310
REV. 1.1, OCT. 01, 2008
1
1 page  
MX25L12805D
DATA PROTECTION
The MX25L12805D are designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transition. During power up the device automatically resets the state machine
in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after
successful completion of specific command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
• Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and
tPUW (internal timer) may protect the Flash.
• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte
boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other
command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
• Software Protection Mode (SPM): by using BP0-BP3 bits to set the part of Flash protected from data change.
• Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP3 bits and SRWD bit from data change.
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all
commands except Release from deep power down mode command (RDP) and Read Electronic Signature command
(RES).
www.Da•taShAedevt4aUn.ccoemd Security Features: there are some protection and securuity features which protect content from inadvertent
write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read
only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible
which may protect various area by setting value of BP0-BP3 bits.
Please refer to table of "protected area sizes".
- The Hardware Proteced Mode (HPM) use WP#/ACC to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.
II. Additional 512-bit secured OTP for unique identifier: to provide 512-bit one-time program area for setting device
unique serial number - Which may be set by factory or system customer. Please refer to table 3. 512-bit secured OTP
definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 512-bit secured OTP by entering 512-bit secured OTP mode (with ENSO command), and going through
normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command
P/N: PM1310
REV. 1.1, OCT. 01, 2008
5
5 Page 
MX25L12805D
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until
next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next
CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The
difference of Serial mode 0 and mode 3 is shown as Figure 3.
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RES and REMS the shifted-in instruction
sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the
following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP, DP, ENSO, EXSO,and WRSCUR, the CS# must
go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and
not affect the current operation of Write Status Register, Program, Erase.
Figure 3. Serial Modes Supported
CPOL CPHA
(Serial mode 0) 0
0 SCLK
(Serial mode 3) 1
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1 SCLK
SI
SO
MSB
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1310
REV. 1.1, OCT. 01, 2008
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX25L12805D.PDF ] | |
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