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부품번호 | MX25L12845E 기능 |
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기능 | 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY | ||
제조업체 | Macronix International | ||
로고 | |||
전체 30 페이지수
MX25L12845E
MX25L12845E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
PRELIMINARY
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P/N: PM1428
REV. 0.06, MAR. 05, 2009
1
MX25L12845E
Figure 38. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Parallel).............. 59
Figure 39. Read Electronic Manufacturer & Device ID (REMS) Sequence (Parallel)............................................ 60
Figure 40. Write Protection Selection (WPSEL) Sequence (Command 68)........................................................... 61
Figure 41. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)............................ 61
Figure 42. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)....................................... 61
Figure 43. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)............................................. 62
Figure 44. Power-up Timing.................................................................................................................................... 63
Table 11. Power-Up Timing and VWI Threshold...................................................................................................... 63
INITIAL DELIVERY STATE...................................................................................................................................... 63
RECOMMENDED OPERATING CONDITIONS......................................................................................................... 64
ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 65
LATCH-UP CHARACTERISTICS............................................................................................................................... 65
ORDERING INFORMATION....................................................................................................................................... 66
PART NAME DESCRIPTION..................................................................................................................................... 67
PACKAGE INFORMATION........................................................................................................................................ 68
REVISION HISTORY ................................................................................................................................................. 69
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P/N: PM1428
REV. 0.06, MAR. 05, 2009
4
4페이지 MX25L12845E
GENERAL DESCRIPTION
MX25L12845E is 134,217,728 bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When it
is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. The MX25L12845E
features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device
is enabled by CS# input.
MX25L12845E provides high performance read mode, which may latch address and data on both rising and falling
edge of clock. By using this high performance read mode, the data throughput may be doubling. Moreover, the per-
formance may reach direct code execution, the RAM size of the system may be reduced and further saving system
cost.
MX25L12845E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on whole chip and
multi-I/O features.
When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and
data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2
pin and SIO3 pin for address/dummy bits input and data Input/Output. Parallel mode is also provided in this device.
It features 8 bit input/output for increasing throughputs. This feature is recommeded to be used for factory produc-
tion purpose.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte),
block (32K-byte/64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC cur-
rent.
The MX25L12845E utilizes MXIC's proprietary memory cell, which reliably stores memory contents even after
www.DataS1h0e0e,t040U0.copmrogram and erase cycles.
Table 1. Additional Features
Additional Protection and Security
Featu-
res
Part Name
Flexible or
Individual block
(or sector)
protection
4k-bit
secured OTP
1 I/O
Read
(104MHz)
2 I/O
Read
(70MHz)
Read
Performance
4 I/O
1 I/O
2 I/O
4 I/O
Read DT Read DT Read DT Read
(70MHz) (50MHz) (50MHz) (50MHz)
8 I/O
Parallel Mode
(6MHz)
MX25L12845E
V
V
VV V V
VV
V
Additional
Featu-
res
Part Name
RES
(command :
AB hex)
MX25L12845E 17 (hex)
REMS
(command :
90 hex)
C2 17 (hex)
(if ADD=0)
Identifier
REMS2
(command :
EF hex)
REMS4
(command :
DF hex)
C2 17 (hex)
(if ADD=0)
C2 17 (hex)
(if ADD=0)
REMS4D
(command :
CF hex)
C2 17 (hex)
(if ADD=0)
RDID
(command:
9F hex)
C2 20 18 (hex)
P/N: PM1428
7
REV. 0.06, MAR. 05, 2009
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구 성 | 총 30 페이지수 | ||
다운로드 | [ MX25L12845E.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
MX25L12845E | 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY | Macronix International |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |