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PDF MX25L12855E Data sheet ( Hoja de datos )
| Número de pieza | MX25L12855E | |
| Descripción | 128M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX25L12855E
MX25L12855E
SECURED SERIAL FLASH SPECIFICATION
PRELIMINARY - PUBLIC
www.DataSheet4U.com
P/N: PM1466
REV. 0.05, MAR. 05, 2009
1
1 page  
PRELIMINARY
MX25L12855E
128M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two I/O mode) structure or 33,554,432 x 4 bits (four I/O
mode) structure
• 4096 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 512 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 256 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.7~3.6V
- Normal read
- 50MHz
- Fast read (Normal Serial Mode)
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 70MHz with 4 dummy cycles
- 4 I/O: 70MHz with 6 dummy cycles
- Fast read (Double Transfer Rate Mode)
www.Da ta S hee-t41U.Ic/Oom: 50MHz with 6 dummy cycles
- 2 I/O: 50MHz with 6 dummy cycles
- 4 I/O: 50MHz with 8 dummy cycles
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously Program mode (automatically increase address under word program mode)
- Fast erase time: 90ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 80s(typ.) /chip
• Low Power Consumption
- Low active read current: 45mA(max.) at 104MHz, 40mA(max.) at 66MHz and 30mA(max.) at 33MHz
- Low active programming current: 25mA (max.)
- Low active erase current: 25mA (max.)
- Low standby current: 100uA (max.)
- Deep power down current: 40uA (max.)
• Typical 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
P/N: PM1466
REV. 0.05, MAR. 05, 2009
5
5 Page 
MX25L12855E
Table 2. Protected Area Sizes
Status bit
BP3 BP2 BP1 BP0
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Protection Area
128Mb
All
All
All
All
All
All
All
All
Upper half (hundrend and twenty-eight blocks: 128 to 255)
Upper quarter (sixty-four blocks: 192 to 255)
Upper eighth (thirty-two blocks: 224 to 255)
Upper sixteenth (sixteen blocks: 240 to 255)
Upper 32nd (eight blocks: 248 to 255)
Upper 64th (four blocks: 252 to 255)
Upper 128th (two blocks: 254 and 255)
None
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0.
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting de-
www.DataShveiceet4Uu.ncoiqmue serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Se-
cured OTP Definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for secu-
rity register bit definition and table of "4K-bit Secured OTP Definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Se-
cured OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
xxx000~xxx00F
xxx010~xxxFFF
Size
128-bit
3968-bit
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
Determined by customer
P/N: PM1466
REV. 0.05, MAR. 05, 2009
11
11 Page | ||
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