|
|
PDF MX25L1635D Data sheet ( Hoja de datos )
| Número de pieza | MX25L1635D | |
| Descripción | 16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH | |
| Fabricantes | Macronix International | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MX25L1635D (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
MX25L1635D
www.DataSheet4U.com
MX25L1635D
DATASHEET
P/N: PM1374
REV. 1.5, OCT. 01, 2008
1
1 page  
MX25L1635D
16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 16M:16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure or 4,194,304 x 4 bits (four I/O read
mode) structure
• 512 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 32 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast read
- 1 I/O: 104MHz & 86MHz with 8 dummy cycles
- 4 I/O: 75MHz with 6 dummy cycles
- 2 I/O: 75MHz with 4 dummy cycles
- Fast access time: 104MHz & 86MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)
- Serial clock of four I/O read mode : 75MHz (15pF + TTL Load), which is equivalent to 300MHz
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously program mode (automatically increase address under word program mode)
- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 14s(typ.) /chip
• Low Power Consumption
www.DataS- hLeoewt4Ua.cctoivme read current: 25mA(max.) at 104MHz & 86MHz, 20mA(max.) at 66MHz and 10mA(max.) at 33MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 20uA (max.)
• Typical 100,000 erase/program cycles
• 10 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions
- Additional 512-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
P/N: PM1374
REV. 1.5, OCT. 01, 2008
5
5 Page 
MX25L1635D
Table 2. Protected Area Sizes
BP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Status bit
BP2 BP1
00
00
01
01
10
10
11
11
00
00
01
01
10
10
11
11
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
NO.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Protect Level
16Mbit block grouping
(none)
(1block, protected block 31th)
(2blocks, protected block 30th-31th)
(4blocks, protected block 28th-31th)
(8blocks, protected block 24th-31th)
(16blocks, protected block 16th-31th)
(32blocks, protected all)
(32blocks, protected all)
(32blocks, protected all)
(32blocks, protected all)
(16blocks, protected block 0th-15th)
(24blocks, protected block 0th-23th)
(28blocks, protected block 0th-27th)
(30blocks, protected block 0th-29th)
(31blocks, protected block 0th-30th)
(32blocks, protected all)
II. Additional 512-bit secured OTP for unique identifier: to provide 512-bit one-time program area for setting device
unique serial number - Which may be set by factory or system customer. Please refer to table 3. 512-bit secured OTP
definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 512-bit secured OTP by entering 512-bit secured OTP mode (with ENSO command), and going through
normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command
to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security register bit
w w w . D adt eafSinhitieone at 4ndU t.acbolemof "512-bit secured OTP definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512-bit secured OTP
mode, array access is not allowed.
Table 3. 512-bit Secured OTP Definition
Address range
Size
xxxx00~xxxx0F
128-bit
Standard
Factory Lock
ESN (electrical serial number)
xxxx10~xxxx3F
384-bit
N/A
Customer Lock
Determined by customer
P/N: PM1374
REV. 1.5, OCT. 01, 2008
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX25L1635D.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MX25L1635D | 16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH | Macronix International |
| MX25L1635E | 16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH | Macronix International |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |