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LG1600FXH2380 데이터시트 PDF




Agere Systems에서 제조한 전자 부품 LG1600FXH2380은 전자 산업 및 응용 분야에서
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부품번호 LG1600FXH2380 기능
기능 LG1600FXH Clock and Data Regenerator
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LG1600FXH2380 데이터시트, 핀배열, 회로
Data Sheet
August 1999
LG1600FXH Clock and Data Regenerator
Figure 1. LG1600FXH Open View
Features
s Integrated clock recovery and data retiming
s Surface-mount package
s Single ECL supply
s Robust FPLL design
s Operation up to BER = 1e–3
s SONET/SDH compatible loss of signal alarm
s High effective Q allows long run lengths
s Jitter tolerance exceeding ITU-T/Bellcore
s Low clock jitter generation: typical <0.005 UI
s Standard and custom data rates
0.50 Gbits/s—5.5 Gbits/s
s Complementary 50 I/Os
Applications
s SONET/SDH receiver terminals and regenerators
OC-12 through OC-96/STM-4 through STM-32
s SONET/SDH test equipment
s Proprietary bit rate systems
s Digital video transmission
s Clock doublers and quadruplers




LG1600FXH2380 pdf, 반도체, 판매, 대치품
LG1600FXH Clock and Data Regenerator
Data Sheet
August 1999
Theory of Operation (continued)
FPD OUT
FPD
OUT
A. fck < fB
TIME
–360°
–180°
0° 180°
360°
PHASE
FPD
OUT
12-3228(F)r.4
Figure 5. Frequency and Phase Detector
Characteristics
The frequency detector is not a separate function but
an integral part of the phase-lock loop. Any transition
between frequency and phase acquisition is completely
avoided. Figure 5 shows the output characteristics of
the FPD, which is essentially an extended range phase
detector. The two quadrature clock phases are used to
produce hysteresis, which extends the phase detector
range to ±270°. The extended range gives the phase
detector a static frequency sensitivity as demonstrated
in Figure 6. For clock frequencies lower than the bit rate
(the phase is increasing), the top trajectory of the dia-
gram in Figure 6 is followed. When the VCO frequency
exceeds the bit rate, the lower trajectory applies. Since
the linear part of the phase detector produces a net-
zero output, in the first instance, positive pulses are fed
into the loop filter increasing the VCO frequency, while
in the latter case, the FPD produces negative pulses.
The wide, 540° range of the phase detector is also
responsible for the high jitter tolerance of the
LG1600FXH and an associated immunity to cycle slip
under high jitter conditions. The clock can be momen-
tarily misaligned as much as 270° but still return to its
original position. This property is extremely important
in synchronous systems, since a cycle slip would cause
misalignment of the demultiplexer following the circuit
resulting in a loss of frame condition. The LG1600FXH
can handle bit error rates up to 1e–3 as a result of low-
frequency jitter.
TIME
B. fck > fB
12-3229(F)r.4
Figure 6. Frequency Detector Operation
PLL Dimensioning
The LG1600FXH CDR employs a heavily damped
second order phase-lock loop. A linear model of this
PLL is depicted in Figure 7. The conventional second-
order equation describing the jitter transfer of the PLL
is shown below:
ϕo 2ςωns + ωn2
H(s) = -ϕ----i (s) = -s---2----+-----2---ς---ω-----n---s----+-----ω----n2-
where ϕi and ϕo denote the input and output phase,
respectively, ς is the PLL damping ratio and ωn is the
natural frequency. For most clock recovery applications
a very high damping is required, that renders the PLL
essentially as a first-order system with a slight peaking
that is generally undesirable. The second-order equa-
tion above does not provide much insight into the peak-
ing and bandwidth parameters.
ϕi
Kd
PHASE DETECTOR
C
Rx
Ko
VCO
ϕo
SUM OF INTERNAL
AND EXTERNAL
LOOP FILTER
CAPACITANCE
12-3230(F)r.5
Figure 7. Phase-Lock Loop Linear Model
4 Lucent Technologies Inc.

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LG1600FXH2380 전자부품, 판매, 대치품
Data Sheet
August 1999
LG1600FXH Clock and Data Regenerator
Pin Information (continued)
The pin descriptions for the LG1600FXH are given in Table 1.
Table 1. Pin Descriptions
Pin
1, 4, 17
7
9
11
14
26
31
35
38
43
48
51
55
60
65
18, 68
2, 3, 5, 6,
8, 10, 12,
13, 15, 16,
19, 20, 21,
22, 23, 24,
25, 27, 28,
29, 30, 32,
33, 34, 36,
37, 39, 40,
41, 42, 44,
45, 46, 47,
49, 50, 52,
53, 54, 56,
57, 58, 59,
61, 62, 63,
64, 66, 67
Body
Symbol
DNC
VREF
CEXT
REXT
LOS
V–CLKO
V+CLKO
VSS
V–OUT
V+OUT
V–FB
V–TH
V–IN
V+IN
V+FB
NIC
GND
Name/Description
Do Not Connect. Internal test point or reserved for future use.
Reference Voltage. Nominally –3.2 V. Can be used to bias LG1605DXB
(see data sheet). Load 10 k.
Terminal for optional external capacitor to increase PLL damping (normally
not connected).
Terminal for external resistor to set PLL bandwidth (Required).
Loss of Signal Indicator. Provides approximately 1 mA sink current with
data signal present, can interface to CMOS, TTL when connected to logic
VDD through a 10 kresistor. Normally grounded when not used.
Recovered Clock Out. ac couple or terminate into 50 to GND.
Recovered Clock Out. ac couple or terminate into 50 to GND.
Supply Voltage. –5.2 Vdc nominal.
Warning: Connecting a positive voltage to this pin will permanently
damage the device.
Regenerated Data Out. ac couple or terminate into 50 to GND.
Regenerated Data Out. ac couple or terminate into 50 to GND.
dc Feedback Voltage. Connect to V–TH.
Input Threshold Voltage. Connect to V–FB.
Negative Data Input. Internally ac coupled.
Positive Data Input. Internally ac coupled.
dc Feedback Voltage. Internally connected; not normally used.
No Internal Connection. May be grounded.
Ground. Connect to top ground plane of coplanar/microstrip circuit board.
GND
Ground. Does not need to be connected. GND pins provide all necessary
ground connections.
Lucent Technologies Inc.
7

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LG1600FXH2380

LG1600FXH Clock and Data Regenerator

Agere Systems
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