|
|
PDF AM79C965A Data sheet ( Hoja de datos )
| Número de pieza | AM79C965A | |
| Descripción | Single-chip 10/100 MBPS Pci Ethernet Controller | |
| Fabricantes | Advanced Micro Systems | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AM79C965A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Am79C965A
PCnet™-32 Single-Chip 32-Bit Ethernet Controller
DISTINCTIVE CHARACTERISTICS
s Single-chip Ethernet controller for 486 and
Video Electronics Standards Association
(VESA) local buses
s Supports ISO 8802-3 (IEEE/ANSI 802.3) and
Ethernet standards
s Direct interface to the 486 local bus or VESA
VL-Bus
s Enhanced burst mode with support for Am486™
burst read/write operations
s Software-compatible with AMD’s Am7990
LANCE, Am79C90 C-LANCE, Am79C960
PCnet-ISA, Am79C961 PCnet-ISA+, Am79C961A
PCnet-ISA II, Am79C970A PCnet-PCI II, and
Am79C900 ILACC™ register and descriptor
architecture
s Compatible with Am2100/Am1500T and Novell
NE2100/NE1500 driver software
s High-performance Bus Master architecture with
integrated DMA buffer management unit for low
CPU and bus utilization
s Built-in byte-swap logic supports both big and
little endian byte alignment
www.DastaSMjhueimcetrp4oUew.rclioermessEdEePsRigOnM interface supports
s Single +5 V power supply operation
s Low-power, CMOS design with sleep modes
allows reduced power consumption for critical
battery-powered applications and Green PCs
s Look-Ahead Packet Processing (LAPP) allows
protocol analysis to begin before end of receive
frame
s Integrated Manchester encoder/decoder
s Individual 136-byte transmit and 128-byte
receive FIFOs provide frame buffering for
increased system latency tolerance and
support the following features:
—Automatic retransmission with no FIFO reload
—Automatic receive stripping and transmit
padding (individually programmable)
—Automatic runt packet rejection
—Automatic deletion of received collision frames
s JTAG Boundary Scan (IEEE 1149.1) test access
port interface for board-level production test
s Provides integrated attachment unit interface
(AUI) and 10BASE-T transceiver with automatic
port selection
s Automatic twisted-pair receive polarity
detection and automatic correction of the
receive polarity
s Optional byte padding to long-word boundary
on receive
s Dynamic transmit FCS generation
programmable on a frame-by-frame basis
s Internal/external loopback capabilities
s Supports the following types of network
interfaces:
—AUI to external 10BASE-2, 10BASE-5,
10BASE-T or 10BASE-F MAU
—Internal 10BASE-T transceiver with Smart
Squelch to twisted-pair medium
s Supports LANCE/C-LANCE/PCnet-ISA general
purpose serial interface (GPSI)
s 160-pin PQFP package
GENERAL DESCRIPTION
The PCnet-32 single-chip 32-bit Ethernet controller is a
highly integrated Ethernet system solution designed to
address high-performance system application require-
ments. It is a flexible bus-mastering device that can be
used in any networking application, including network-
ready PCs, printers, fax modems, and bridge/router
designs. The bus-master architecture provides high
data throughput in the system and low CPU and bus
utilization. The PCnet-32 controller is fabricated with
AMD’s advanced low-power CMOS process to provide
low operating and standby current for power-sensitive
applications.
Publication# 18219 Rev: D Amendment/0
Issue Date: August 2000
1 page  
SLAVE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
VESA VL-BUS MODE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
BUS MASTER AND BUS SLAVE DATA BYTE PLACEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
BUFFER MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
RE-INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
BUFFER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
DESCRIPTOR RINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
DESCRIPTOR RING ACCESS MECHANISM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
POLLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
TRANSMIT DESCRIPTOR TABLE ENTRY (TDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
RECEIVE DESCRIPTOR TABLE ENTRY (RDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
MEDIA ACCESS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TRANSMIT AND RECEIVE MESSAGE DATA ENCAPSULATION . . . . . . . . . . . . . . . . . . . . . . . . 91
MEDIA ACCESS MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MANCHESTER ENCODER/DECODER (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
EXTERNAL CRYSTAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
EXTERNAL CLOCK DRIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
MENDEC TRANSMIT PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TRANSMITTER TIMING AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
RECEIVER PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
INPUT SIGNAL CONDITIONING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
CLOCK ACQUISITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
PLL TRACKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
CARRIER TRACKING AND END OF MESSAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
DATA DECODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
JITTER TOLERANCE DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ATTACHMENT UNIT INTERFACE(AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
DIFFERENTIAL INPUT TERMINATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
COLLISION DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
TWISTED-PAIR TRANSCEIVER (T-MAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
TWISTED PAIR TRANSMIT FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
TWISTED PAIR RECEIVE FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LINK TEST FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
POLARITY DETECTION AND REVERSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
TWISTED PAIR INTERFACE STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
www.DataSheet4U.cCoOmLLISION DETECT FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SIGNAL QUALITY ERROR (SQE) TEST (HEARTBEAT) FUNCTION . . . . . . . . . . . . . . . . . . . . . . 99
JABBER FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10BASE-T INTERFACE CONNECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
BOUNDARY SCAN CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
TAP FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SUPPORTED INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
INSTRUCTION REGISTER AND DECODING LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
OTHER DATA REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EADI (EXTERNAL ADDRESS DETECTION INTERFACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
GENERAL PURPOSE SERIAL INTERFACE (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
POWER SAVINGS MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SOFTWARE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
I/O RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
I/O REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
HARDWARE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
PCNET-32 CONTROLLER MASTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SLAVE ACCESS TO I/O RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
EEPROM MICROWIRE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Am79C965A
5
5 Page 
PIN DESIGNATIONS: VESA VL-BUS MODE
Listed by Pin Name
Name
ADR2
ADR3
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
ADR10
ADR11
ADR12
ADR13
ADR14
ADR15
ADR16
ADR17
ADR18
ADR19
ADR20
ADR21
ADR22
ADR23
ADR24
ADR25
ADR26
www.DaAtaDSRh2e7et4U.com
ADR28
ADR29
ADR30
ADR31
ADS
AVDD1
AVDD2
AVDD3
AVDD4
AVSS1
AVSS2
BE0
BE1
BE2
Pin No.
Name
24 BE3
22 BLAST
21 BRDY
19 CI+
18 CI–
16 D/C
15 DAT0
14 DAT1
13 DAT2
12 DAT3
10 DAT4
9 DAT5
7 DAT6
6 DAT7
5 DAT8
4 DAT9
150 DAT10
149 DAT11
148 DAT12
146 DAT13
145 DAT14
144 DAT15
143 DAT16
141 DAT17
140 DAT18
138 DAT19
137 DAT20
134 DAT21
133 DAT22
132 DAT23
45 DAT24
126 DAT25
131 DAT26
115 DAT27
110 DAT28
123 DAT29
117 DAT30
53 DAT31
52 DI+
50 DI–
Pin No.
47
32
34
130
129
48
99
98
96
94
93
92
90
88
87
86
85
84
82
78
77
76
75
73
72
71
70
68
66
64
63
62
61
60
58
57
56
55
128
127
Name
DO+
DO–
DVDD1
DVDD2
DVDD3
DVDDCLK
DVDDO1
DVDDO2
DVDDO3
DVDDO4
DVDDO5
DVSS1
DVSS2
DVSS3
DVSS4
DVSSCLK
DVSSN1
DVSSN2
DVSSN3
DVSSN4
DVSSN5
DVSSN6
DVSSN7
DVSSN8
DVSSN9
DVSSN10
DVSSN11
DVSSN12
DVSSN13
DVSSN14
DVSSN15
DVSSPAD
EECS
EEDI/LNKST
EEDO/LEDPRE3/SRD
EESK/LED1/SFBD
INTR1
INTR2/EAR
INTR3/TDI
INTR4/TMS
Pin No.
Name
125 JTAGSEL
124 LB/VESA
26 LBS16
95 LCLK
135 LDEV
30 LEADS
8 LED2/SRDCLK
35 LGNT
65 LGNTO/TCK
91 LRDY
142 LREQ
37 LREQI/TDO
69 M/IO
107 NC
136 NC
28 NC
3 NC
11 NC
17 NC
23 NC
51 NC
59 NC
67 NC
74 NC
83 NC
89 RDYRTN
97 RESET
103 RXD+
139 RXD–
147 SHFBUSY
158 SLEEP
20 TXD+
157 TXD–
154 TXP+
152 TXP–
155 VLBEN
151 W/R
105 WBACK
104 XTAL1
102 XTAL2
Pin No.
106
153
25
29
38
27
2
33
101
43
36
100
46
1
39
40
41
79
80
81
119
120
121
122
160
42
49
109
108
159
156
114
112
113
111
31
44
54
116
118
Am79C965A
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM79C965A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AM79C965A | Single-chip 10/100 MBPS Pci Ethernet Controller | Advanced Micro Systems |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |