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PDF LTC2905 Data sheet ( Hoja de datos )
| Número de pieza | LTC2905 | |
| Descripción | (LTC2904 / LTC2905) Precision Dual Supply Monitors | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2905 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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FEATURES
■ Monitors Two Inputs Simultaneously
■ Nine Threshold Combinations
■ Three Supply Tolerances (5%, 7.5%, 10%)
■ Guaranteed Threshold Accuracy: ±1.5% of
Monitored Voltage Over Temperature
■ Internal VCC Auto Select
■ Power Supply Glitch Immunity
■ 200ms Reset Time Delay (LTC2904 Only)
■ Adjustable Reset Time Delay (LTC2905 Only)
■ Open Drain RST Output
■ Guaranteed RST for V1 ≥ 1V or V2 ≥ 1V
■ Low Profile (1mm) SOT-23 (ThinSOTTM) and Plastic
(3mm x 2mm) DUFN Packages
APPLICATIO S
■ Desktop and Notebook Computers
■ Handheld Devices
■ Network Servers
■ Core, I/O Monitor
, LTC and LT are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
LTC2904/LTC2905
Precision Dual Supply Monitors
with Pin-Selectable Thresholds
DESCRIPTIO
The LTC®2904/LTC2905 are dual supply monitors in-
tended for systems with two supply voltages. The dual
supply monitors have a common reset output with delay
(200ms for the LTC2904 and adjustable using an external
capacitor for the LTC2905). This product provides a
precise, space-conscious and micropower solution for
supply monitoring.
The LTC2904/LTC2905 feature a tight 1.5% threshold
accuracy over the whole operating temperature range,
and glitch immunity to ensure reliable reset operation
without false triggering. The open drain RST output is
guaranteed to be in the correct state for inputs down to 1V.
The LTC2904/LTC2905 also feature three programming
input pins, which program the threshold and tolerance
level without requiring any external components. These
three programming pins provide a total of 27 different
voltage level and tolerance combinations, eliminating
the need to have different parts for development and
implementation of different systems with different voltage
levels requiring monitoring function.
wwwT.DYataPShIeCetA4UL.comAPPLICATIO
5V, 3.3V Dual Supply Monitor with 5% Tolerance
5V
DC/DC
SYSTEM
CONVERTER
3.3V
LOGIC
0.1µF
V1 V2
LTC2905
S1 TMR
S2 GND
TOL RST
0.1µF
22nF
29045 TA01
Table 1. Voltage Threshold Programming
V1 V2 S1 S2
5.0 3.3 V1 V1
3.3 2.5 Open GND
3.3 1.8 V1 Open
3.3 1.5 Open V1
3.3 1.2 Open Open
2.5 1.8 GND GND
2.5 1.5 GND Open
2.5 1.2 GND V1
2.5 1.0 V1 GND
sn29045 29045fs
1
1 page  
LTC2904/LTC2905
TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C unless otherwise noted.
IV2 vs Temperature
20.0
V1 = 2.5V
V2 = 3.3V
19.5 S1 = S2 = TOL = 1.4V
19.0
18.5
18.0
17.5
17.0
–50 –25 0 25 50 75 100
TEMPERATURE (°C)
29045 G10
Reset Time-Out Period (tRST)
vs Temperature
235
CRT = 22nF
230 (FILM)
225
220
215
210
205
www.Da2t0a0Sheet4U.com
195
–50 –25 0 25 50
TEMPERATURE (°C)
75 100
29045 G13
RST Output Voltage vs V1
5
V2 = S1 = S2 = TOL = V1
10pF CAPACITOR AT RST
4
3
2
1
0
–1
01 2 345
V1 (V)
29045 G16
Typical Transient Duration vs
Comparator Overdrive (V1, V2)
700
600
500
400 RESET OCCURS
ABOVE CURVE
300
200
100
0
0.1 1
10 100
COMPARATOR OVERDRIVE VOLTAGE (% OF VRTX)
29045 G11
RST Output Voltage vs V1
5
V2 = S1 = S2 = TOL = V1
10k PULL-UP RESISTOR
4
3
2
1
0
–1
01
23
V1 (V)
45
29045 G14
RST Pull-Down Current (IRST)
vs Supply Voltage (VCC)
V2 = S1 = S2 = TOL = V1
5 NO PULL-UP R
4
RST AT 150mV
3
2
1 RST AT 50mV
0
01 2 345
SUPPLY VOLTAGE, VCC (V)
29045 G17
Reset Time Out Period (tRST)
vs Capacitance (CTMR)
10000
1000
100
10
1
0.1
10p
100p 1n 10n
CTMR (FARAD)
100n 1µ
29045 G12
RST Output Voltage vs V1
5
V2 = S1 = S2 = TOL = V1
10k PULL-UP RESISTOR
4
3
2
1
0
–1
01
23
V1 (V)
45
29045 G15
RST Pull-Down Current (IRST)
vs Supply Voltage (VCC)
S1 = V2 = V1
5 TOL = S2 = GND
NO PULL-UP R
4
3
RST AT 150mV
2
1 RST AT 50mV
0
01 2 345
SUPPLY VOLTAGE, VCC (V)
29045 G18
sn29045 29045fs
5
5 Page 
LTC2904/LTC2905
APPLICATIO S I FOR ATIO
Figure 1 shows the desired delay time as a function of the
value of the timer capacitor that should be used:
10000
1000
100
10
1
0.1
10p
100p 1n 10n
CTMR (FARAD)
100n 1µ
29045 F01
Figure 1. Reset Time-Out Period vs Capacitance
Leaving the TMR pin open with no external capacitor
generates a reset time-out of approximately 200µs. For
long reset time-out, the only limitation is the availability of
large value capacitor with low leakage. The TMR capacitor
will never charge if the leakage current exceeds the mini-
mum TMR charging current of 2.1µA (typical).
RST and RST Output Characteristics
www.DataSheet4U.com
The DC characteristics of the RST and RST pull-up and
pull-down strength are shown in the Typical Performance
Characteristics section. Both RST and RST have a weak
internal pull-up to VCC = Max (V1, V2) and a strong pull-
down to ground.
The weak pull-up and strong pull-down arrangement allow
these two pins to have open-drain behavior while possess-
ing several other beneficial characteristics.
The weak pull-ups eliminate the need for external pull-up
resistors when the rise time on these pins is not critical. On
the other hand, the open-drain RST configuration allows
for wired-OR connections and can be useful when more
than one signal needs to pull down on the RST line.
As noted in the Power-Up and Power-Down sections the
circuits that drive RST and RST are powered by VCC.
During fault condition, VCC of at least 1V guarantees a
maximum VOL = 0.4V at RST. However, at VCC = 1V the
weak pull-up current on RST is barely turned on. There-
fore, an external pull-up resistor of no more than 100k is
recommended on the RST pin if the state and pull-up
strength of the RST pin is crucial at very low VCC.
Note however, by adding an external pull-up resistor, the
pull-up strength on the RST pin is increased. Therefore, if
it is connected in a wired-OR connection, the pull-down
strength of any single device needs to accommodate this
additional pull-up strength.
Output Rise and Fall Time Estimation
The RST and RST outputs have strong pull-down capabil-
ity. The following formula estimates the output fall time
(90% to 10%) for a particular external load capacitance
(CLOAD):
tFALL ≈ 2.2 • RPD • CLOAD
where RPD is the on-resistance of the internal pull-down
transistor estimated to be typically 40Ω at room tempera-
ture (25°C) and CLOAD is the external load capacitance on
the pin. Assuming a 150pF load capacitance, the fall time
is about 13ns.
The rise time, on the RST and RST pins is limited by weak
internal pull-up current sources to VCC. The following
formula estimates the output rise time (10% to 90%) at the
RST and RST pins:
tRISE ≈ 2.2 RPU • CLOAD
where RPU is the on-resistance of the pull-up transistor.
Notice that this pull-up transistor is modeled as a 6µA
current source in the Block Diagram as a typical represen-
tation.
The on-resistance as a function of the VCC = Max (V1, V2)
voltage (for VCC > 1V) at room temperature is estimated as
sn29045 29045fs
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC2905.PDF ] | |
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