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PDF AS3SSD8GB8PBG Data sheet ( Hoja de datos )
| Número de pieza | AS3SSD8GB8PBG | |
| Descripción | Solid State Disk On Chip | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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AUSTIN SEMICONDUCTOSRO, ILNICD. STATE DISK
PRELIMINARY
Austin Semiconductor, Inc.
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
Solid State Disk On Chip
(SSDoC)
FEATURES
• Capacities
- 4 GB
- 8 GB
- 16 GB
• PATA Compatibility
- ATA-5 compatible
- UDMA4 supported
- PIO Mode 4 supported
- MWDMA Mode 2 supported
• Performance
- Sustained Sequential Read Bandwidth:16 MB/s
- Sustained Sequential Write Bandwidth: 5 MB/s
• Form Factor
- BGA Package
• 31 mm (W) x 31 mm (L) x 4.2-7.8 mm (H)
• Weighs approximately 11 grams (TYP)
• Each NAND component, either a 4, 8 or 16Gb
device, based on the use of single and stacked
silicon solutions
• ECC correction = 6 Bytes within a 512 Byte
sector
www.Da•taASuhetoetm4Ua.ctoicm sleep mode
• Controller contained in base interposer
• SLC (Single-Level Cell) NAND Flash
• Reliability
- Mean Time Between Failure (MTBF)
>2,000,000 Hours (est.)
- Program/Erase >1,000,000 Times (est.)
- Temp Cycle 500/1000 cycles, JEDEC A104
Condition B -55ºC to +125ºC
• Power Supply Voltage: 5.0V or 3.3 V ± 10%
(TYP)
• Power Consumption (Vcc = 5.0 V)
- Idle: 10 mW (TYP)
- Active: 255 mW (TYP)
• Operating Temperature
- Commercial: 0C to 70C
- Industrial: -45C to 85C
• Shock and Vibration
- Shock: 1500G MIL-STD0810F
- Vibration: 15 G RMS MIL-STD0810F
• Compliances
- Lead free
- RoHS
- Sn/Pb Ball Option
OVERVIEW
The solid state disk is based on a proprietary
package stacking technology to create an extremely
space conscious, robust Solid State Disk. The SSD
is capable of operating in harsh, vibration prone
product platforms such embedded computing
applications, heavy transportation, ultra portables,
handhelds, mobile computing, digital
radio, high-speed networking & enterprise
applications, as well as, military, aerospace and
industrial applications.
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
AUSTIN SEMICONDUCTOSRO, ILNICD. STATE DISK
PRELIMINARY
Austin Semiconductor, Inc.
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
OPERATING CONDITIONS (continued)
Recommended Operating Conditions
Operating Temperature and Voltages
Parameter
Symbol Max. Typ Min. Unit
Industrial: 0oC to +70oC
T0 0
- 70 oC
Commercial: -40oC to +85oC T0 0
- 70 oC
Vcc supply voltage
Tcc_P 4.5 5 5.5
Tcc_P 3.0 3.3 3.6
V
V
Ground supply voltage
GndPLN 0 0 0 V
DC Characteristics (PATA controller configuration)
Symbol
Paramenter
VIL Input LOW Voltage
VIH Input HIGH Voltage
VOL Output LOW Voltage
www.DataShVeeOtH4U.comOutput HIGH Voltage
Operating Current, VCC_R=5.0V
ICC Sleep Mode
Operating, 20 MHz
Operating, 40 MHz
Operating Current, VCC_R=3.3V
ICC Sleep Mode
Operating, 20 MHz
Operating, 40 MHz
ILI Input Leakage Current
ILO Output Leakage Current
CI/O Input / Output Capacitance
Min.
-0.3
2.2
2.4
Max.
+0.8
Vcc+0.3
0.45
Units
V
V
V
V
Conditions
IOL=4mA
IOH=-1mA
0.2 mA
30 mA
50 mA
.02 m
30 m
50 m
±10 μA
±10 μA
10 pF
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
AUSTIN SEMICONDUCTOSRO, ILNICD. STATE DISK
PRELIMINARY
Austin Semiconductor, Inc.
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
SIGNAL DESCRIPTIONS
g
Symbol
Type
Description
IDE_A0
Output
Address bus
IDE_A1
Output
IDE_A2
Output
IDE_D0
Input/Output Data bus. The signals D15..D0 represent the bidirectional
IDE_D1
Input/Output data bus; active high signals a "one".
IDE_D2
Input/Output
IDE_D3
Input/Output
IDE_D4
Input/Output
IDE_D5
Input/Output
IDE_D6
Input/Output
IDE_D7
Input/Output
IDE_D8
Input/Output
IDE_D9
Input/Output
IDE_D10
Input/Output
IDE_D11
Input/Output
IDE_D12
Input/Output
IDE_D13
Input/Output
IDE_D14
Input/Output
IDE_D15
Input/Output
IDE_INTRQ
Output
Drive interrupt request.
I/O Data Write Enable is the strobe signal asserted by the
host to write device registers or the data port.
DIOW shall be negated by the host prior to the initiation of
IDE_IOWR\
Input
an Ultra DMA burst. STOP shall be negated by the host
www.DataSheet4U.com
before the data is transferred in an Ultra DMA burst. The
assertion of STOP by the host during an Ultra DMA burst
signals the termination of the Ultra DMA burst.
IDE_IORD\
Input
I/O Data Read Enable is the strobe signal asserted by the
host to read device registers or the data port.
IDE_CS0\
Input
Drive chip select 0 is used by host to select Command
Block registers.
IDE_CS1\
Input
Drive chip select 1 is used by host to select Command
Block registers.
IDE_PIOIS16\
Output
16-bit I/O transfer.
IDE_PDIG
Input/Output Passed diagnostics.
DMA request. This signal, used for DMA data transfers
between host and device, shall be asserted by the device
when it is ready to transfer data to or from the host. For
IDE_DMARQ
IDE_DMARQ\
Output
multi word DMA transfers, the direction of data transfer is
Controller by IDE_IORD\ and IDE_IOWR\. When a DMS
operation is enabled, CS0\ and CS1\ shall not be asserted
and transfers shall be 16 bits wide. This signal shall be
release when the device is not selected.
FC_WAIT
Output
Ready signal to IDE_IORDY
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
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