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부품번호 | BIT3715 기능 |
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기능 | High Performance PWM Controller | ||
제조업체 | Beyond Innovation Technology | ||
로고 | |||
Beyond Innovation Technology Co., Ltd.
BIT3715
BIT3715
High Performance PWM Controller
www.DataSheet4U.com
Preliminary
Version: 0.00
Please read the notice stated in this preamble carefully before
accessing any contents of the document attached.
Admission of BiTEK’s statement therein is presumed once the
document is released to the receiver.
碩頡科技 BiTEK
管 December 20, 2005 制
DCC CONTROLLED
‘05/11/30 Preliminary
Confidential, for authorized user only
page 1 of 11
Beyond Innovation Technology Co., Ltd.
BIT3715
Pin Description:
Table 1
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
www.DataSheet4U.com
14
15
16
Symbol
INN
CMP
LOAD
CTOSC
TIMER
ONOFF
GND
OUT1
OUT2
VDD
PWMOUT
CTPWM
PWMDC
OUTADJ
ISEN
MODSEL
I/O Descriptions
I The inverting input of the error amplifier.
O Output of the error amplifier.
A switch that connected to the high frequency triangle wave generator.
I/O
This switch is open while the voltage level of ISEN pin is lower than 1.3V.
external resistor connected here may change the operation frequency of
An
CTOSC in open load situation.
I/O
An external capacitor connected here decides the frequency of high
frequency PWM controller.
With internal reference current and an external capacitor connected here, it
decides the required period of starting and the timing of initialization. The
controller is forced to the reset mode while the voltage level of TIMER is lower
than 0.3V. During reset mode, the current about 60uA will flow into the INN
I/O pin to reduce the output level of the error amplifier CMP to turn off the
controller. The protection function will be enabled after this node is charged
to exceed 2.5V. The output current of this pin is 20uA when the level of
TIMER is lower than 0.3V. The output current becomes 1uA when the level
of TIMER is higher than 0.3V
I
The control pin of turning on or off the IC. 1V threshold with an internal 80K±
15% ohm pull-low resistor.
I/O The ground pin of the device.
O The active high output driver.
O The active low output driver.
I The power supplies pin of the device.
The output pin of low frequency PWM generator. A 2.5V or floating two state
O output is provided through this pin. The internal circuit limits the max.
Duty-cycle to about 92%.
With the internal reference current and an external capacitor connected here
I/O can set the operation frequency of low frequency PWM generator with 1.0V ~
2.5V triangle wave output.
Low frequency PWM controlling input. A PWM output comes out by
I comparing this DC input and the 1.0 ~ 2.5V triangle wave that is generated by
CTPWM.
Output regulation and protection. If a > 2.0 V voltage is detected. A ~ 60uA
I current will flow into the INN pin to adjust the output of the error amplifier pin
CMP to regulate the output voltage.
I
Load current detection pin, the open load situation is detected if a less than
1.3V input is sensed.
O To set the output polarity of the low frequency PWM generator.
‘05/11/30 Preliminary
碩頡科技 BiTEK
管 December 20, 2005 制
DCC CONTROLLED
Confidential, for authorized user only
page 4 of 11
4페이지 Beyond Innovation Technology Co., Ltd.
DC/AC Characteristics
Table 4
Parameter
Test Conditions Min.
Supply Voltages
Pin VDD input
Chip Consumed Current
8V Supply Voltage
Ta=25°C
4.0
Error Amplifier Reference Voltage
Non-Inverting
amplifier
input
of
the
error Measure INN
Line regulation
VDD=4.0~8.0 V
1.2125
Under Voltage Look Out
Positive Going Threshold
Ta=25°C
Hysteresis
Note3
The 1st High Frequency Ramp Wave Generator
Operating Frequency
Output peak(CTOSC)
Note1
Output valley(CTOSC)
3.8
0.1
50
Error Amplifier
Input voltage
Open loop gain
Unit gain band width
Note2
0.1
60
1
Power On Initialization and Latched Off Protection Enable
Pin TIMER Output current
Case1. TIMER <0.3V
Pin TIMER Output current
Case1. TIMER > 0.3V
VDD=6V, Ta=25°C
Power On Reset/Initialization Note 3
threshold on pin TIMER
Latched Off Protection enable
threshold on pin TIMER
Load Detection
Pin ISEN detection lower threshold VDD=6V, Ta=25°C
Hysterisis
Output Detection and Adaptive Adjusting
Pin OUTADJ detection lower
threshold
Hysterisis
VDD=6V, Ta=25°C
www.DataSheet4U.coImNN pin pull-up current source
The 2nd Low Frequency PWM Generator
Ramp Wave Peak(CTPWM)
Ramp Wave Valley(CTPWM)
PWM Frequency
Control voltage of 0 % Duty cycle
on pin PWMDC
Case 1. MODSEL = 0V
Control voltage of 0 % Duty cycle VDD=6V, Ta=25°C
on pin PWMDC
Case 1. MODSEL = ICVDD
Output voltage of Pin PWMOUT
for making the logic “high”.
Pin PWMOUT output for making
the logic “low”
Maximum Duty Cycle
Output of the 1st PWM (OUT1, OUT2)
CMOS output impedance
(Note2, Note3)
Rising Time
VDD=6V,
Falling Time
2000pF(Note2,
Delay Time
Note3)
10
BIT3715
Typ.
4
Max.
8.0
Unit
V
mA
1.25 1.2875
2 20
V
mV
4.0 4.2
0.2 0.3
V
V
400 KHz
2.25 V
0.5 V
3V
80 dB
1.5 MHz
20 uA
1 uA
0.3 V
2.5 V
1.3 V
20 mV
2.0 V
20 mV
60 uA
2.5 V
1.0 V
100K
Hz
1.0 V
2.5 V
2.5 V
Floating
92碩 頡 科 技 %B i T E K
50管 Decembero2h0m, 2005 制
110 nS
10D0 CC CONTnRS OLLED
600 nS
‘05/11/30 Preliminary
Confidential, for authorized user only
page 7 of 11
7페이지 | |||
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