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MFRC522 데이터시트 PDF




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부품번호 MFRC522 기능
기능 Standard performance MIFARE and NTAG frontend
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MFRC522 데이터시트, 핀배열, 회로
MFRC522
Standard performance MIFARE and NTAG frontend
Rev. 3.9 — 27 April 2016
112139
Product data sheet
COMPANY PUBLIC
1. Introduction
This document describes the functionality and electrical specifications of the contactless
reader/writer MFRC522.
Remark: The MFRC522 supports all variants of the MIFARE Mini, MIFARE 1K,
MIFARE 4K, MIFARE Ultralight, MIFARE DESFire EV1 and MIFARE Plus RF
identification protocols. To aid readability throughout this data sheet, the MIFARE Mini,
MIFARE 1K, MIFARE 4K, MIFARE Ultralight, MIFARE DESFire EV1 and MIFARE Plus
products and protocols have the generic name MIFARE.
1.1 Differences between version 1.0 and 2.0
The MFRC522 is available in two versions:
MFRC52201HN1, hereafter referred to version 1.0 and
MFRC52202HN1, hereafter referred to version 2.0.
The MFRC522 version 2.0 is fully compatible to version 1.0 and offers in addition the
following features and improvements:
Increased stability of the reader IC in rough conditions
An additional timer prescaler, see Section 8.5.
A corrected CRC handling when RX Multiple is set to 1
This data sheet version covers both versions of the MFRC522 and describes the
differences between the versions if applicable.
2. General description
The MFRC522 is a highly integrated reader/writer IC for contactless communication
at 13.56 MHz. The MFRC522 reader supports ISO/IEC 14443 A/MIFARE and NTAG.
The MFRC522’s internal transmitter is able to drive a reader/writer antenna designed to
communicate with ISO/IEC 14443 A/MIFARE cards and transponders without additional
active circuitry. The receiver module provides a robust and efficient implementation for
demodulating and decoding signals from ISO/IEC 14443 A/MIFARE compatible cards and
transponders. The digital module manages the complete ISO/IEC 14443 A framing and
error detection (parity and CRC) functionality.
The MFRC522 supports MF1xxS20, MF1xxS70 and MF1xxS50 products. The MFRC522
supports contactless communication and uses MIFARE higher transfer speeds up to
848 kBd in both directions.




MFRC522 pdf, 반도체, 판매, 대치품
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
6. Block diagram
The analog interface handles the modulation and demodulation of the analog signals.
The contactless UART manages the protocol requirements for the communication
protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data
transfer to and from the host and the contactless UART and vice versa.
Various host interfaces are implemented to meet different customer requirements.
ANTENNA
ANALOG
INTERFACE
CONTACTLESS
UART
FIFO
BUFFER
Fig 1. Simplified block diagram of the MFRC522
REGISTER BANK
SERIAL UART
SPI
I2C-BUS
HOST
001aaj627
MFRC522
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.9 — 27 April 2016
112139
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 95

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MFRC522 전자부품, 판매, 대치품
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
Table 3.
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin description …continued
Symbol
Type[1] Description
VMID
P internal reference voltage
RX I RF signal input
AVSS
G analog ground
AUX1
O auxiliary outputs for test purposes
AUX2
O auxiliary outputs for test purposes
OSCIN
OSCOUT
I
O
crystal oscillator inverting amplifier input; also the input for an externally generated clock
(fclk = 27.12 MHz)
crystal oscillator inverting amplifier output
IRQ O interrupt request output: indicates an interrupt event
SDA
I/O I2C-bus serial data line input/output[2]
NSS
I SPI signal input[2]
RX I UART address input[2]
D1 I/O test port[2]
ADR_5
I/O I2C-bus address 5 input[2]
D2 I/O test port
ADR_4
I
I2C-bus address 4 input[2]
D3 I/O test port
ADR_3
I
I2C-bus address 3 input[2]
D4 I/O test port
ADR_2
I
I2C-bus address 2 input[2]
D5 I/O test port
ADR_1
I
I2C-bus address 1 input[2]
SCK
I SPI serial clock input[2]
DTRQ
O UART request to send output to microcontroller[2]
D6 I/O test port
ADR_0
I
I2C-bus address 0 input[2]
MOSI
I/O SPI master out, slave in[2]
MX O UART output to microcontroller[2]
D7 I/O test port
SCL
I/O I2C-bus clock input/output[2]
MISO
I/O SPI master in, slave out[2]
TX O UART data output to microcontroller[2]
EA I external address input for coding I2C-bus address[2]
[1] Pin types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground.
[2] The pin functionality of these pins is explained in Section 8.1 “Digital interfaces”.
[3] Connection of heatsink pad on package bottom side is not necessary. Optional connection to pin DVSS is possible.
MFRC522
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.9 — 27 April 2016
112139
© NXP Semiconductors N.V. 2016. All rights reserved.
7 of 95

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